ADC/DAC
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LTC2220IUP-1 - 12-Bit 185Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2220IUP-1 is a 12-bit, 185 Msps pipelined analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package with exposed pad, designed for digitizing high-frequency, wide-dynamic-range signals. The device features 67.5 dB SNR to 140 MHz input, 80 dB spurious-free dynamic range (SFDR) to 170 MHz input, and a 775 MHz full-power bandwidth sample-and-hold, making it well suited for demanding communications and IF-sampling applications. The converter operates from a single 3.3 V supply with a typical power dissipation in the 660-890 mW range depending on sample rate. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes, enabling downstream processing by DSPs, FPGAs, or microcontrollers. Within the broader signal chain hierarchy, the ADC sits between the analog front end (amplifiers, filters) and the digital processing block. Pipelined ADCs in particular use a multi-stage architecture that delivers high sample rates (tens to hundreds of Msps) with moderate resolution (10-14 bits), making them the workhorse for wireless baseband, radar, test instrumentation, and software-defined radio. Key features of the LTC2220IUP-1 include differential or single-ended input flexibility, parallel CMOS/CMOS-compatible output, integrated bandgap reference, and an optional output dither mode for improved SFDR at small input levels. The pipelined architecture provides inherent sample-and-hold operation, eliminating the need for an external SHA. The 64-QFN exposed-pad package provides a low thermal-resistance path, allowing the device to operate at the industrial -40C to +85C range without additional heatsinking at typical power levels. Typical applications include cellular base-station receiver IF digitization, cable-modem downstream capture, high-end medical imaging front ends, test and measurement digitizers, and radar/sonar signal processing. The 775 MHz analog input bandwidth also enables direct IF sampling of signals in the 70-200 MHz range, simplifying the receiver chain by eliminating a down-conversion stage. When designing with this part, allocate adequate PCB area for the exposed pad and stitch its thermal vias to an internal ground plane. The analog input pins should be DC-biased through a common-mode network; bypassing must use low-ESR ceramic capacitors placed within 5 mm of the supply pins. Output data timing is referenced to an external clock, and trace-length matching on the output bus is critical to maintain setup/hold margins above 100 Msps. This page synthesizes distributor pricing, pin-compatible drop-in alternatives from the LTC2220 family, and practical PCB layout notes not collected in the manufacturer datasheet alone. All specifications are extracted from the Linear Technology/Analog Devices LTC2220 datasheet and DigiKey listing as of 2026-10-13.
LTC2221CUP - 12-Bit 135Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2221CUP is a 12-bit, 135Msps pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package. It combines 67.5 dB SNR and 80 dB SFDR with a 775 MHz full-power bandwidth sample-and-hold front end, all on a single 3.3 V supply while dissipating 660 mW. The C-suffix denotes the commercial 0 °C to +70 °C temperature grade, and the UP suffix designates the plastic 64-pin QFN-9x9 (MO-220-WNJR-5) exposed-pad package. An ADC (analog-to-digital converter) is a semiconductor device that transforms continuous analog signals into discrete digital codes at a defined sample rate. Pipelined ADCs such as the LTC2221CUP use a multi-stage switched-capacitor architecture to balance high sample rate, wide analog input bandwidth, and low power - positioning them between successive-approximation (SAR) ADCs and high-speed flash converters in the data-converter hierarchy. They are the standard building block for digitizing IF, baseband, and wideband intermediate-frequency signals in communications and instrumentation. Key performance features include 67.5 dB SNR up to 140 MHz input, 80 dB spurious-free dynamic range (SFDR) up to 170 MHz input, and 775 MHz full-power sample-and-hold bandwidth. The differential input architecture, internal bandgap reference, and optional external reference support simplify board design. LVDS/CMOS-compatible digital outputs and an integrated duty-cycle stabilizer further ease FPGA/ASIC interfacing. The pipelined architecture uses 6 to 8 cascaded 1.5-bit stages with digital error correction, latency is fixed at 5 clock cycles, and the internal reference is trimmed for low drift over temperature. The 775 MHz sample-and-hold amplifier comfortably digitizes signals beyond the second Nyquist zone, enabling undersampling for IF digitization. Typical applications include cellular base-station receivers, cable-headend downstreams, test and measurement digitizers, medical imaging, and radar/sonar intermediate-frequency capture. The wide input bandwidth makes the LTC2221CUP particularly attractive for undersampling architectures where the analog input is well above half the sample rate. When designing, decouple the AVDD, DVDD, and DRVDD rails with separate 0.1 µF + 10 µF ceramic networks placed within 5 mm of each pin, and tie the exposed pad (EP) to a clean analog ground plane for thermal dissipation (660 mW steady-state). This page combines distributor pricing, drop-in alternative cross-references, and engineering design notes not aggregated on a single manufacturer page.
LTC2221IUP - 12-Bit 135Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2221IUP is a 12-bit, 135Msps pipelined analog-to-digital converter (ADC) in a 64-lead 9x9 mm QFN (UP) package. It features a single analog input channel, on-chip sample-and-hold, and an integrated high-bandwidth track-and-hold amplifier designed for IF undersampling applications up to 100MHz. The 1ku list price starts from $55.26 according to Analog Devices. A pipelined ADC is a high-speed analog-to-digital conversion architecture that uses multiple cascaded low-resolution stages to achieve high sampling rates while keeping die area and power manageable. Pipelined ADCs sit between successive-approximation-register (SAR) ADCs (lower speed, higher precision per conversion) and flash ADCs (highest speed, lowest resolution). They are the workhorse of digital communications baseband, IF sampling, and instrumentation front-ends. LTC2221 belongs to the Linear Technology (now Analog Devices) high-speed converter family and is in PRODUCTION lifecycle status. Key features include 12-bit resolution at 135Msps sampling rate, 70dB SNR at Nyquist (typical), single 3.3V supply operation, and LVDS or CMOS-compatible outputs. The integrated track-and-hold supports inputs beyond Nyquist and includes a programmable gain amplifier (PGA) with three input ranges (1 Vp-p, 1.5 Vp-p, 2 Vp-p). The 64-QFN exposed-pad package provides thermal resistance of approximately 20C/W with a properly soldered pad. Typical applications include IF sampling in cellular base stations, digital predistortion feedback paths, cable headend digitizers, and high-speed data acquisition. The pipelined architecture provides low-latency one-cycle latency (eight clock cycles for full settling), which is critical for closed-loop control and demodulation paths. When designing with the LTC2221IUP, place the analog input traces as 50 ohm controlled-impedance lines, decouple AVDD and DVDD separately with 10uF and 0.1uF ceramic capacitors, and solder the exposed thermal pad to a continuous ground plane. The encode clock must be a low-jitter source (<1 ps RMS) to preserve SNR.
LTC2222CUK-11 - 105Msps 11-Bit ADC, 48-QFN | Analog Devices
The Analog Devices LTC2222CUK-11 is an 11-bit, 105 Msps pipelined analog-to-digital converter housed in a 48-pin QFN (7x7 mm) package. It samples at 105 Msps with 65.4 dB SNR (to 140 MHz input), 80 dB SFDR (to 150 MHz input), and a 775 MHz full-power bandwidth sample-and-hold. The device operates from a single 3.3 V supply and dissipates approximately 475 mW, with CMOS-compatible digital outputs. A pipelined ADC is a multi-stage converter that interleaves sample-and-hold and residue amplifier blocks to digitize analog signals at high speed while maintaining resolution. In the wider signal-chain hierarchy, the LTC2222CUK-11 sits between a front-end analog amplifier/buffer (typically an RF transformer or op-amp driver) and downstream digital processing - a DSP, FPGA, or custom ASIC - making it a critical high-speed bridge in communications, instrumentation, and imaging systems. The -11 derivative delivers 11-bit resolution (rather than the 12-bit native LTC2222) when cost or data-rate scaling is more important than absolute ENOB. Key differentiating features include 0.15 ps RMS ultra-low aperture jitter, which enables accurate undersampling of IF frequencies in communications receivers, single 3.3 V operation that simplifies board power design, and CMOS outputs that interface directly with ASICs and FPGAs without level shifters. The 7x7 mm 48-QFN exposed-pad package provides low thermal resistance for sustained full-rate operation. Applications for this part include cellular base-station IF sampling, cable-headend downstream QAM digitizers, test-and-measurement bench instruments, ultrasound beamforming front ends, and software-defined radio receivers. It is widely used wherever a moderately priced, low-jitter ADC serves as the analog-domain gateway into a digital signal-processing engine. When designing with this ADC, allocate a low-noise LDO for the analog AVDD rail because high-frequency sampling current transients couple directly into the reference ladder; a 1uF + 0.1uF ceramic bypass on the ADC reference pins must be placed within 2 mm of the package. This page synthesizes distributor pricing, drop-in alternatives, and practical decoupling guidance not assembled in the manufacturer datasheet alone.
LTC2222IUK-11 - 11-Bit 105Msps ADC | Analog Devices
The Analog Devices LTC2222IUK-11 is an 11-bit, 105 Msps pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm, UK package) with exposed pad, optimized for high-frequency, wide-dynamic-range signal acquisition. It samples at up to 105 Msps with a 775 MHz full-power input bandwidth and operates from a single 3.3 V rail while drawing only 475 mW of power. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a specified sampling rate, serving as the bridge between the analog front-end (amplifiers, filters, transducers) and the digital signal processor, FPGA, or microcontroller. The pipelined ADC architecture used in the LTC2222IUK-11 enables high sampling rates with low power by processing each sample through a cascade of low-resolution stages, balancing speed, resolution, and die area efficiently. Within the signal-chain hierarchy, the ADC sits after the anti-alias filter and before the digital decimator or processor. Key features include 65.4 dB SNR and 80 dB SFDR for input frequencies up to 150 MHz, selectable ±0.5 V or ±1 V input ranges, no missing codes over temperature, optional clock duty-cycle stabilizer, and shutdown/nap modes for power management. The integrated sample-and-hold amplifier and CMOS-compatible outputs simplify interface to FPGAs and ASICs. The pipelined architecture of the LTC2222IUK-11 uses multi-bit per-stage conversion with digital error correction, achieving low spurious content and high linearity while operating at 105 Msps. The clock duty-cycle stabilizer relaxes the timing requirement on the external encode clock source, allowing use of lower-cost oscillators without degrading AC performance. Typical applications include wideband communications receivers, IF sampling in software-defined radio, cable head-end equipment, digital oscilloscopes, and medical imaging front-ends. The wide input bandwidth makes it suitable for undersampling IF architectures in cellular base-station designs. A key design consideration is providing a low-jitter encode clock and proper RF layout around the analog inputs to achieve the rated SNR; thermal management of the exposed pad is also important at full sampling rate.
LTC2226HLU#PBF - 12-bit 25Msps ADC, 32-TQFP | Analog Devices
The Analog Devices LTC2226HLU#PBF is a 12-bit, 25 Msps pipelined analog-to-digital converter (ADC) housed in a 32-pin TQFP (5 mm × 5 mm) surface-mount package. It delivers ±0.3 LSB INL (typical), ±0.15 LSB DNL (typical), 71.4 dB SNR, 90 dB SFDR, and operates from a single 3 V supply drawing only 75 mW. The 'LU' suffix denotes the TQFP-32 plastic package (MS-026), and '#PBF' designates lead-free / RoHS-compliant lead finish. An ADC (analog-to-digital converter) is a data converter IC that samples a continuous analog voltage and produces a discrete binary code proportional to the input. Pipelined ADCs like the LTC2226 are the dominant architecture for sample rates between 5 Msps and 250 Msps because they balance high throughput, low power, and small die area. Within the converter hierarchy, the LTC2226 sits under: ADC -> data converter -> signal-chain IC -> mixed-signal semiconductor. It is part of a pin-compatible family (LTC2246 at 14-bit, LTC2226 at 12-bit), enabling resolution swaps on the same PCB. Key features include a flexible 1 Vp-p to 2 Vp-p differential or single-ended analog input range, an integrated sample-and-hold amplifier with 575 MHz full-power bandwidth, a duty-cycle-stabilized clock input, shutdown and nap power-save modes, and no-missing-codes over temperature. The 0.25 LSB RMS transition noise sets a low noise floor relative to full scale. Architecturally, the LTC2226 uses a multi-stage switched-capacitor pipeline with digital error correction, fed by an internal or external reference. A separate output supply rail (OVdd, 0.5 V to 3.6 V) lets the CMOS outputs interface directly to 1.8 V, 2.5 V, or 3.3 V logic without level shifters. Typical applications include communications IF/baseband digitizers, portable instrumentation, CCD/camera imaging pipelines, ultrasound front-ends, and radar/digitizer cards. The wide input bandwidth and 75 mW dissipation suit battery-powered field equipment. A primary design consideration is the analog input network: a low-noise differential driver (such as the LT6600 or AD8138) feeding a properly terminated transformer preserves the SFDR rating. Decoupling requires 0.1 µF ceramics close to AVdd and OVdd with a 10 µF bulk cap at the board entry. This page consolidates distributor price, drop-in 32-TQFP alternatives, and design notes not found in the manufacturer datasheet alone.
LTC2227IUH - 12-Bit 40Msps Low Power 3V ADC | Analog Devices
The Analog Devices LTC2227IUH is a 12-bit, 40 Msps pipelined analog-to-digital converter (ADC) optimized for low-power 3V operation, housed in a 32-pin QFN (5x5 mm) package with an exposed thermal pad. It delivers 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, consuming approximately 135 mW from a single 3V analog supply. An ADC (analog-to-digital converter) is a data converter integrated circuit that samples a continuous-time analog signal and outputs a discrete-time digital code proportional to the input amplitude. Pipelined ADCs like the LTC2227IUH use a multi-stage architecture with per-stage flash sub-ADCs and digital error correction, enabling high sampling rates (tens to hundreds of Msps) at moderate resolution (10-14 bits) while dissipating far less power than full-flash architectures. Within the converter taxonomy, the LTC2227IUH sits as: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features include a pipelined architecture with digital error correction, fully differential input stage with adjustable common-mode voltage, selectable internal bandgap reference (2.5V or optional external reference), and CMOS-compatible parallel output bus. The differential input accepts both single-ended and fully differential drive, simplifying front-end design with op-amps or transformers for communication and imaging front-ends. The 32-lead QFN (5x5 mm) exposed-pad package provides a low thermal resistance path to the PCB ground plane, allowing sustained 40 Msps operation at 3V without additional cooling. The pin-compatible LTC2228 (65 Msps) and LTC2226 (25 Msps) variants in the same QFN-32 footprint let designers scale dynamic performance without re-laying out the PCB. Typical applications include cellular basestation receiver IF digitizers, handheld imaging systems, portable oscilloscopes and digital storage scopes, cable head-end equipment, and spectrum analyzers. The low 135 mW dissipation also suits battery-powered instrumentation such as ultrasound front-ends and portable radar digitizers. When designing with this converter, place the analog input coupling network and the internal reference bypass capacitor as close as possible to the AVDD and REFH/REFL pins. Treat the digital outputs as 40 Msps switching signals - route them over a continuous ground plane and keep them away from the analog input traces to avoid digital feedback into the sample-and-hold. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single canonical reference for the LTC2227IUH.
LTC2228IUH - 12-Bit 65Msps 3V ADC, 32-QFN | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2228IUH is a 12-bit, 65 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals from a single 3 V supply. Packaged in a 32-lead QFN (5x5 mm) with exposed pad, the LTC2228IUH delivers ±0.3 LSB INL (typical), ±0.15 LSB DNL (typical), no missing codes over temperature, and 0.25 LSB RMS transition noise, making it well suited for demanding imaging and communications signal chains. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog input and produces a discrete-time digital code proportional to the input voltage. Pipelined ADCs like the LTC2228 split the conversion into cascaded low-resolution stages with digital error correction, enabling high sample rates (>10 MHz) at moderate resolution (10-14 bits). They sit within the broader taxonomy of data-converter IC -> mixed-signal IC -> semiconductor device, and they are the interface between analog front-ends and digital signal processors, FPGAs, or ASICs. Key features of the LTC2228IUH include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, guaranteeing spectral purity for cellular baseband, IF sampling, and portable instrumentation applications. The device accepts a single-ended CLK input that controls converter operation and conversion start, simplifying board layout by removing the need for a complementary clock. A separate output supply pin (OVDD) lets the outputs swing between 0.5 V and 3.6 V, allowing direct connection to 1.8 V, 2.5 V, or 3.3 V logic families without level shifters. Typical applications for the LTC2228IUH include cellular baseband transceiver IF sampling, ultrasound and medical imaging front-ends, portable and battery-powered test instrumentation, CCD imaging digitizers, and cable-head-end digital receivers. Its low 3 V power consumption makes it attractive for power-constrained designs, while the wide AC performance margin accommodates broadband signals up to the Nyquist band. When designing with the LTC2228IUH, place the input network as close as possible to the analog input pin and provide a low-jitter clock source - the SNR budget at 65 Msps degrades by approximately 1 dB for every 1 ps of clock jitter. Decouple OVDD and AVDD separately with 0.1 µF ceramic capacitors near the pins, and tie the exposed pad to a clean analog ground plane for thermal and electrical performance. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not collated in the manufacturer datasheet, providing information gain beyond what distributor or manufacturer product pages offer.
LTC2230CUP - 10-Bit 170Msps ADC | Analog Devices | QFN-64
The Analog Devices LTC2230CUP is a 10-bit, 170 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, UP) package with exposed pad. It features a single differential input, an internal 2.5V reference (selectable from internal/external), and CMOS-compatible logic outputs. Per the Analog Devices product page, samples are rated at 1ku pricing starting from $39.66. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed Nyquist ADC architecture that processes a continuous stream of samples through cascaded low-resolution stage flash converters, each stage resolving a portion of the bits before passing the residue to the next stage. Pipelined ADCs sit within the broader taxonomy of data converters (ADC -> Nyquist ADC -> pipelined ADC -> mixed-signal IC -> semiconductor) and are the dominant architecture for high-sample-rate applications in the 10 Msps to several hundred Msps range where successive-approximation (SAR) ADCs run out of speed. The LTC2230 family represents a mainstream 10-bit pipelined design optimized for IF undersampling, imaging, and instrumentation. Key features include 170 Msps sample rate, 10-bit resolution, ±1 LSB INL (typical), 60 dB SNR at Nyquist with 5MHz input, and a single 3V supply operation (2.7V to 3.4V). Power dissipation is approximately 380 mW at full sample rate. The differential input range supports a 1V P-P full-scale swing using the internal 2.5V reference, or can be driven with external reference for gain fine-tuning. The UP package has an exposed thermal pad that must be soldered to the PCB ground plane for thermal dissipation and electrical performance. Design-in considerations include the requirement for low-jitter clock input (less than 0.5 ps RMS for full ENOB), differential input drive via transformer or op-amp driver, and proper decoupling of the analog and digital supplies (they share the same 3V rail but require separate bypass networks). For comparison, the LTC2240 family extends the same architecture to 12-bit resolution, and the LTC2220 family drops to 105 Msps in the same QFN-64 (UP) footprint.
LTC2237IUH - 10-Bit 40Msps Low-Noise 3V ADC | Analog Devices
The Analog Devices LTC2237IUH is a 10-bit, 40 Msps low-noise 3V analog-to-digital converter designed for digitizing high-frequency, wide-dynamic-range signals. It comes in a 32-pin QFN (5mm x 5mm) plastic package with exposed pad, and operates from a single 3V analog supply plus a separate 0.5V to 3.6V digital output supply. According to the manufacturer datasheet, DC accuracy specifications include ±0.1 LSB INL (typical) and ±0.05 LSB DNL (typical), with ±0.5 LSB INL/DNL guaranteed over temperature, and a low 0.07 LSB RMS transition noise. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them to discrete digital codes, enabling real-world analog signals to be processed by digital systems. The LTC2237 family belongs to the SAR/pipeline hybrid high-speed converter category, sitting within the broader hierarchy of data converter -> mixed-signal IC -> semiconductor. The 3V single-supply operation makes the family a power-efficient choice for portable and battery-driven imaging or communication platforms. Key features of the LTC2237IUH include 40 Msps sampling rate, 10-bit resolution, a separate output supply pin allowing direct interface to 0.5V-3.6V logic, integrated PGA/frontend input structure with internal reference, and shutdown/sleep modes for power-sensitive applications. The 78 dB SNR and 85 dB SFDR (typical) are well-matched to imaging pipelines and intermediate-frequency (IF) signal chains. The low 0.07 LSB RMS transition noise enables clean capture of small-swing analog inputs without code-edge flicker. Architecturally the device uses a pipelined multi-stage converter core with on-chip sample-and-hold and an internal bandgap reference. Internal register setting controls the input span (1Vpp or 2Vpp), giving designers flexibility to optimize SNR against full-scale headroom. The 3V analog supply combined with CMOS digital outputs keeps the typical power dissipation low, which is a major advantage over 5V-supply predecessors when designing thermally-constrained boards. Typical applications include medical imaging front-ends, digital oscilloscopes, IF/baseband signal processing in communications receivers, and CCD/CMOS image sensor digitizers. The wide input bandwidth and 78 dB SNR make it well suited for undersampling IF signals in software-defined radio receivers and for high-speed CCD line-scan capture in industrial inspection. The separate logic supply simplifies connection to modern FPGAs and DSPs without level translators. When designing with the LTC2237IUH, drive the analog input with a low-impedance differential amplifier (such as the AD8138) to preserve SFDR at high input frequencies, and place the input anti-alias filter as close to the analog input pins as possible. Decouple the exposed pad to a solid ground plane to keep junction temperature within the -40C to +85C industrial range. This page synthesizes verified distributor pricing, drop-in alternative MPNs, application guidance, and PCB/thermal design notes not found in the manufacturer datasheet alone.
LTC2240IUP-10 - 10-Bit 170Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2240IUP-10 is a 10-bit, 170 Msps pipelined analog-to-digital converter housed in a 64-lead QFN (UP, 9x9 mm) package with exposed pad. It is designed for digitizing high-frequency, wide dynamic-range signals and features 60.6 dB SNR and 80 dB SFDR at the rated sample rate, making it well suited to demanding communications, IF-sampling, and instrumentation front-ends. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes the analog input through a cascade of low-resolution flash stages, each handling a subset of the bits and feeding a residue to the next stage. This parallelism allows sample rates from tens of MSPS to several hundred MSPS with low power consumption and high dynamic range, sitting at the top of the speed hierarchy below flash ADCs but above successive-approximation (SAR) and delta-sigma converters. Pipelined ADCs are the workhorse of communications infrastructure, radar, test equipment, and digital oscilloscopes. Key specifications of the LTC2240IUP-10 include a 170 Msps maximum sample rate, 10-bit resolution, 1.4 GHz analog input bandwidth, single 3V supply operation (2.85V to 3.4V), and LVDS or CMOS compatible digital outputs. The device integrates an internal sample-and-hold, programmable gain amplifier, and internal reference, simplifying board-level design and reducing external component count. The architecture uses a multi-stage pipelined core with digital error correction, achieving low latency and excellent spurious-free dynamic range (SFDR) for narrowband and wideband inputs alike. Differential clock inputs and flexible output clocking allow easy interface to FPGAs and dedicated clock-generation ICs. Typical applications include cellular basestation receivers, cable head-end equipment, medical imaging, radar IF digitizers, and high-speed data acquisition. The wide analog input bandwidth also makes the part suitable for direct-IF sampling in software-defined radio (SDR) designs. A key design consideration is the clock jitter budget. Because SNR degrades with aperture uncertainty at high input frequencies, pair the LTC2240IUP-10 with a low-jitter clock source (sub-200 fs rms) and follow standard high-speed ADC layout practices with a solid ground plane and properly bypassed analog/digital domains. This page synthesizes distributor pricing from DigiKey and Mouser, drop-in LTC22xx family alternatives already on XAIPART, and practical design notes not consolidated in the manufacturer datasheet.
LTC2240IUP-12 - 12-Bit 170Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2240IUP-12 is a 12-bit, 170 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide-dynamic-range signals, housed in a 64-lead 9x9 mm QFN package with exposed pad (UP suffix). It features 65.6 dB SNR and 80 dB spurious-free dynamic range (SFDR) at the full 170 Msps sampling rate, with selectable parallel CMOS or LVDS output data interfaces for flexible downstream FPGA or ASIC connection. The differential analog input accepts up to 2 Vp-p full-scale signals, and the device operates from a single 3.3 V analog supply plus a separate 3.3 V or optional 1.8 V digital output supply for reduced digital noise coupling. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts real-world analog voltages into discrete digital codes at a sampling rate, serving as the interface between RF/analog front ends and digital signal processors. Within the broader signal-chain taxonomy, the LTC2240IUP-12 sits in the high-speed pipeline ADC category (12-bit resolution, 100+ Msps), which sits under successive-approximation and flash architectures for sampling rates up to several hundred Msps. In the system hierarchy, pipeline ADCs occupy the tier between general-purpose SAR ADCs (<=10 Msps) and ultra-high-speed interleaved or JESD204B-class ADCs (>500 Msps). Key features of the LTC2240IUP-12 include a 65.6 dB signal-to-noise ratio, 80 dB SFDR at 170 Msps with a 70 MHz input, and an aperture jitter of 0.15 ps RMS, making it suitable for undersampling IF signals in communications receivers. The device supports full-power analog input bandwidth above 500 MHz and offers programmable gain and offset adjustment via dedicated SPI pins, with an internal bandgap reference and integrated input common-mode bias. Power dissipation is 638 mW typical at 170 Msps with CMOS outputs and scales downward at lower clock rates. The LTC2240IUP-12 uses a multi-stage pipelined architecture with proprietary input sample-and-hold and digital error correction, allowing it to maintain 12-bit linearity and low spurious content across Nyquist input frequencies. The differential input structure provides common-mode rejection, and the LVDS output option enables high-data-rate transfer over long PCB traces without EMI issues. An internal duty-cycle stabilizer compensates for clock-source non-50 percent duty cycle, simplifying clock-tree design in FPGA-based systems. Typical applications include cellular base-station receiver IF digitizers, cable-headend downstream QAM demodulators, radar and phased-array signal acquisition, medical imaging front ends, and high-speed data-acquisition cards for test and measurement. It also fits spectrum analyzer and software-defined radio ADC positions where 12-bit dynamic range at 170 Msps is sufficient. When designing with this ADC, pay close attention to analog input network design: use a transformer-coupled or differential op-amp driver with appropriate input common-mode biasing, and provide a low-noise clock source with jitter below 0.5 ps RMS to preserve SNR. The exposed pad of the 64-QFN must be soldered to a continuous ground plane to achieve the rated thermal performance and to provide the necessary ground return for the input stage. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design guidance that complement the official Analog Devices datasheet for procurement and engineering decisions.
LTC2241CUP-10 - 10-Bit 210Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2241CUP-10 is a 10-bit, 210 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals in demanding communications and instrumentation applications. Housed in a 64-lead 9x9 mm QFN package, the part delivers 60.5 dB SNR and 78 dB SFDR with ultralow 95 fs RMS aperture jitter that enables accurate IF-frequency undersampling. It operates from a single 2.5 V supply, drawing only 585 mW of power, and supports LVDS, CMOS, or demultiplexed CMOS output modes for flexible digital interface to processors, FPGAs, or ASICs. A 1.2 GHz full-power sample-and-hold bandwidth supports input signals well into the second Nyquist zone. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes for downstream processing by DSPs, microcontrollers, or FPGAs. Within the converter family hierarchy, the LTC2241-10 belongs to the pipelined-architecture sub-type, which uses multiple low-resolution stages to balance sample rate and resolution, sitting between successive-approximation (SAR) converters (low speed, high accuracy) and flash converters (very high speed, low resolution). Pipelined ADCs dominate the 10-200 Msps + 8-16 bit design space used in communications infrastructure, medical imaging, and test equipment. Key features include selectable input ranges of ±0.5 V or ±1 V, no-missing-codes guaranteed over the full operating range, optional clock duty-cycle stabilizer for jitter-sensitive systems, and dedicated shutdown/nap power-saving modes. The 64-QFN package integrates the exposed pad for thermal dissipation and a clean analog/digital ground split. The data-ready output clock simplifies downstream FPGA data capture timing. Typical applications include cellular base-station receiver IF digitizers, cable-headend downstream/upstream QAM demodulators, digital oscilloscope front ends, medical ultrasound beam-former channels, radar/sonar IF sampling, and software-defined radio (SDR) platforms where wideband undersampling is required. The pin-compatible LTC2242-10 family member extends the offering to 250 Msps for systems that need extra timing headroom on the same PCB layout.
LTC2241CUP-12 - 12-Bit 210Msps ADC | Analog Devices | 64-QFN
The Analog Devices LTC2241CUP-12 is a 12-bit, 210 Msps pipelined analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic-range signals. It is offered in a 64-pin QFN (9 mm x 9 mm) package with an exposed thermal pad, and provides a single differential analog input channel optimized for IF/RF sampling. According to the manufacturer datasheet (224112fc.pdf), the part delivers 65.5 dB SNR and 78 dB SFDR with ultralow 95 fs-RMS aperture jitter, making it suitable for IF undersampling in demanding communications systems. A pipelined ADC is a high-speed data converter architecture that uses multiple low-resolution flash stages in cascade to digitize an analog input at sample rates from tens of megasamples per second to over a gigasample per second. Pipelined ADCs trade slightly higher latency for the ability to convert very wide analog input bandwidths, and they are the workhorse of communications infrastructure, oscilloscopes, and software-defined radio front ends. The LTC2241CUP-12 belongs to the broader hierarchy of ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key specifications include 12-bit native resolution, 210 Msps guaranteed conversion rate, 65.5 dB SNR, 78 dB SFDR, 95 fs-RMS jitter, and an integrated input PGA that is bypassable for full-scale input ranges of 1.0 Vp-p to 1.6 Vp-p. The differential analog input is sampled on a clock edge from an external CMOS/LVDS/TTL-compatible encode input, and the output is an offset-binary or two's-complement parallel CMOS bus. A separate output supply (OVDD) lets the digital bus interface directly to 1.8 V to 3.3 V logic. Architecturally, the LTC2241CUP-12 uses 12 pipelined 1.5-bit stages with proprietary digital error correction, providing both gain and offset trim registers for system-level calibration. An optional clock duty-cycle stabilizer maintains stable internal bias across varying encode duty cycles, and an optional data-randomizer reduces on-board EMI by spreading the switching noise of the output bus over a wider frequency range. Typical applications include cellular basestation IF sampling, cable-headend digitizers, radar and EW receivers, spectrum analyzer and oscilloscope front ends, and medical ultrasound beamformers. In each of these, the part's combination of 78 dB SFDR and 95 fs-RMS jitter preserves dynamic range even when undersampling high-IF carriers. When laying out the PCB, treat the 64-QFN exposed pad as the primary thermal path and bond it to a continuous ground plane with low-inductance vias to suppress digital switching noise coupling back into the analog input. Provide separate analog and digital supply domains and decouple them with ferrite beads rather than sharing a single ground pour.
LTC2241IUP-12 - 12-Bit, 210Msps ADC | Analog Devices
The Analog Devices LTC2241IUP-12 is a 12-bit, 210 Msps sampling pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals, housed in a 64-pin QFN (UP, 9x9 mm, HVQCCN) surface-mount package. According to the Analog Devices datasheet (224112fc), it delivers 65.5 dB SNR and 78 dB SFDR, with ultra-low 95 fsRMS aperture jitter that enables excellent IF undersampling performance for communications systems. An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes at a specified sampling rate; in the LTC2241IUP-12's case, the pipelined multi-stage architecture allows multi-hundred-MHz sampling while maintaining low latency and high spurious-free dynamic range, occupying the high-performance tier of the converter hierarchy (ADC -> data converter -> signal-chain IC -> mixed-signal semiconductor). The pipeline sub-class trades modest pipeline latency for high throughput and excellent AC linearity, making it the dominant architecture for digital oscilloscopes, software-defined radio, and wideband radar front-ends. Key features of the LTC2241IUP-12 include a single 1.8 V analog supply (with the IUP industrial-temperature grade covering -40 °C to +85 °C), LVDS-compatible or CMOS-selectable digital outputs, an internal high-precision bandgap reference with bypass, and a flexible analog input front end supporting both single-ended and differential drive modes. The 9x9 mm 64-lead HVQCCN (QFN) exposed-pad package offers a thermally enhanced path for the internal 5 W-class analog front end. Typical applications include cellular base-station receivers (digitizing intermediate-frequency signals at 140 MHz or higher), cable-headend DOCSIS downstream capture, digital oscilloscopes, wideband test instrumentation, and IF undersampling receivers for military and aerospace signal-intelligence systems. The part is also used in medical imaging front-ends (ultrasound beamformers) where its high dynamic range supports sensitive detection. When designing with this device, follow the reference layout in the datasheet carefully: provide separate analog and digital ground planes joined at a single star point beneath the exposed pad, use controlled-impedance differential traces for the analog input, and route LVDS outputs with 100 Ω differential termination. Decouple the analog supply with 10 µF ceramic in parallel with 0.1 µF X7R placed within 5 mm of each supply pin, and isolate the conversion clock with a low-jitter PLL or clock-cleaner IC such as the AD9516 to fully exploit the 95 fs aperture jitter. This page synthesizes distributor stock and pricing data, drop-in and pin-compatible alternatives within the LTC2241 family, and practical layout guidance not consolidated in the manufacturer datasheet alone, giving engineers a single-source starting point for evaluation and PCB bring-up.
LTC2242CUP-10 - 10-Bit 250Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2242CUP-10 is a 10-bit, 250 Msps pipelined analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals, housed in a 64-lead QFN (9x9 mm) package with exposed pad. The converter delivers 60.5 dB SNR and 78 dB SFDR at the full 250 Msps sample rate from a single 2.5 V analog supply, and supports LVDS, CMOS, or demultiplexed CMOS output interfaces for flexible downstream FPGA/ASIC interconnect. What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a converter architecture that uses multiple low-resolution flash stages in cascade, with each stage converting a portion of the input while the next stage samples the residue. This architecture achieves high sample rates (tens to hundreds of Msps) at moderate resolution (8-14 bits) with low latency and small die area. Pipelined ADCs sit in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. They are the workhorse of communications infrastructure, radar, and test instrumentation where digitizing IF/RF signals at high dynamic range is required. Key differentiating specifications include 95 fsRMS aperture jitter (enabling excellent IF undersampling noise performance), 1.2 GHz full-power input bandwidth, and 740 mW typical power dissipation. The pipelined core is preceded by a wideband track-and-hold, supporting AC-coupled or DC-coupled single-ended differential inputs through an external driver. A separate output supply (1.5 V to 3.3 V) decouples the noisy digital supply from the analog domain. Typical applications include cellular basestation receivers, cable modem head-ends, radar and lidar digitizers, medical imaging front-ends, and high-speed data acquisition cards. The 78 dB SFDR makes the LTC2242-10 particularly suitable for multi-carrier communications where intermodulation distortion directly limits channel capacity. When designing with this device, allocate a quiet analog ground plane and decouple AVDD with 10 uF tantalum in parallel with 0.1 uF ceramic placed within 5 mm of the supply pins. The exposed thermal pad must be soldered to a ground copper pour of at least 1 square inch to keep junction temperature rise within safe limits at full 250 Msps operation.
LTC2242IUP-10 - 10-Bit, 250Msps ADC, Industrial Temp | Analog Devices
The Analog Devices LTC2242IUP-10 is a 10-bit, 250 Msps pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with exposed thermal pad. It features 60.5 dB SNR, 78 dB SFDR, 1.2 GHz full-power bandwidth sample-and-hold, and 740 mW power dissipation on a single 2.5 V supply. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a quantized digital code. The 250 Msps class belongs to the high-speed pipelined ADC family, used in applications where bandwidth, latency, and dynamic range must be balanced. Within the broader taxonomy, LTC2242IUP-10 is a member of: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipeline ADCs are the workhorse of communications, radar, and test instrumentation front ends. Key differentiating specifications include 60.5 dB SNR and 78 dB SFDR for high-frequency signal capture, 1.2 GHz full-power input bandwidth that exceeds the Nyquist limit and simplifies front-end anti-aliasing, and selectable LVDS / CMOS / demultiplexed CMOS output modes for direct FPGA or ASIC interfacing. The integrated encode clock duty-cycle stabilizer relaxes clock-source jitter requirements, easing system timing design. The device uses a multi-stage switched-capacitor pipeline architecture with on-chip reference and sample-and-hold, enabling low-latency conversion at full sample rate. Industrial temperature grade (-40C to +85C) and 9x9 mm exposed-pad QFN-64 package support dense PCB layouts with effective thermal dissipation up to 740 mW. Typical applications include cellular base-station receivers, cable modem head-ends, test and measurement digitizers, medical imaging, and high-speed radar digitizing front ends. The LVDS output mode is preferred for >150 MHz clock distribution and EMC-sensitive designs. When designing, route analog and digital grounds separately and stitch them only at the exposed pad; place a 2.2 uF X7R bypass close to the supply pins. The encode input should be AC-coupled with the on-chip 100 ohm termination engaged to preserve SNR. This page synthesizes distributor pricing, drop-in alternatives, and design notes not consolidated on the manufacturer datasheet, giving engineers a single-page reference for selection and sourcing.
LTC2242IUP-12 - 12-Bit, 250Msps ADC | Analog Devices
The Analog Devices LTC2242IUP-12 is a 12-bit, 250 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) exposed-pad package, engineered for digitizing high-frequency, wide dynamic-range signals. The ADC delivers 65.4 dB SNR and 78 dB SFDR at the Nyquist input, plus 60.5 dB SNR per the QFN-64 datasheet characteristics, with ultralow 95 fs RMS aperture jitter that enables IF undersampling with excellent noise performance. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, serving as the critical interface between the analog front-end (amplifiers, mixers, sensors) and the digital back-end (FPGA, DSP, processor). High-speed pipeline ADCs at the 100-500 Msps tier are widely used in communications, test and measurement, and defense systems where signal fidelity at IF and baseband frequencies is paramount. Key features of the LTC2242IUP-12 include a 1.2 GHz full-power input bandwidth sample-and-hold, single 2.5 V supply operation, low 740 mW power consumption, plus selectable LVDS, CMOS, or demultiplexed CMOS output formats for flexible FPGA/DSP/ASIC interfacing. The exposed-pad QFN-64 package enables efficient thermal dissipation for the 740 mW dissipation, allowing sustained operation at the 250 Msps full sample rate in compact layouts. The device utilizes a multi-stage pipelined architecture with proprietary calibration, achieving an excellent linearity/spec tradeoff versus lower-speed successive-approximation register (SAR) ADCs. The ultralow jitter enables undersampling of IF frequencies well above the Nyquist limit, relaxing the analog anti-alias filter design and reducing analog front-end cost. Internal references and a flexible clock input simplify board-level integration. Typical applications include cellular basestation receivers, software-defined radios, set-top box and cable infrastructure, test and measurement instrumentation, and radar/sonar intermediate-frequency digitizers. The wide input bandwidth makes the LTC2242IUP-12 particularly attractive for undersampling leading signals where the analog front-end cost dominates. When designing with this ADC, provide a low-noise, low-jitter clock encode to minimize aperture-jitter degradation of SNR, and follow Analog Devices recommended PCB layout for the exposed pad to maintain the 740 mW thermal budget. Output format selection (LVDS vs CMOS) should be chosen to match the downstream FPGA/ASIC capability. This page synthesizes distributor pricing, drop-in same-package alternatives, and design considerations not found in the manufacturer datasheet to accelerate component selection.
LTC2245IUH - 14-Bit 10Msps Low Power ADC | Analog Devices
The Analog Devices LTC2245IUH is a 14-bit, 10 Msps, low-power 3V analog-to-digital converter (ADC) housed in a 32-pin QFN (5 mm x 5 mm) package with exposed pad. It delivers 74.4 dB SNR and 90 dB SFDR at input frequencies well beyond Nyquist, while consuming only 60 mW of power from a single 3V supply. A pipelined ADC is a high-speed converter architecture that uses cascaded low-resolution flash stages to achieve high sampling rates with moderate power and die size. It sits inside the broader hierarchy: ADC -> data converter -> signal chain IC -> analog/mixed-signal semiconductor. Pipelined ADCs dominate 5-200 Msps applications where successive-approximation (SAR) ADCs cannot achieve the required throughput. Key features include ±1 LSB INL (typical), ±0.5 LSB DNL (typical), no missing codes over temperature, 575 MHz full-power input bandwidth, single-ended/differential input range up to 2 Vp-p, clock duty cycle stabilizer, and shutdown/nap power-down modes. The flexible input supports both single-ended and differential drive, allowing direct coupling to IF/RF signals or baseband amplifiers. The LTC2245IUH uses an internal sample-and-hold with 575 MHz bandwidth and a multi-stage pipelined core with proprietary error correction. The 32-QFN (UH) package exposes the die pad for low thermal resistance; total power dissipation is only 69 mW, enabling multi-channel data acquisition systems that cannot tolerate the heat of conventional 100+ Msps converters. Typical applications include high-end imaging, ultrasound front-end digitization, communications IF sampling, and portable test-and-measurement instruments. The wide input bandwidth and low power make it especially suitable for handheld spectrum analyzers and battery-powered communication receivers where thermal budget is tight. When designing with this device, place the analog input traces as short and symmetrical as possible, decouple the 3V supply with a 10 µF tantalum in parallel with 0.1 µF ceramic, and tie the exposed pad (pin 33) to a clean analog ground plane to minimize noise coupling. This page synthesizes distributor pricing, drop-in 32-QFN alternatives, and practical layout guidance that are not collected in the manufacturer datasheet alone.
LTC2246HLU#PBF - 14-Bit 25Msps Low-Power ADC | Analog Devices
The Analog Devices LTC2246HLU#PBF is a 14-bit, 25 Msps, low-power 3V analog-to-digital converter (ADC) in a 32-lead TQFP (5 mm x 5 mm) package, designed for digitizing high-frequency, wide-dynamic-range signals. The pipelined architecture delivers a single differential or single-ended input channel with 74.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, making it suitable for demanding imaging and communications front-ends. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts a continuous analog input voltage into a discrete digital code. Pipelined ADCs in particular use a multi-stage architecture with sample-and-hold front ends and per-stage flash sub-ADCs to achieve high sampling rates at moderate power. Within the power-management and data-acquisition hierarchy, this part sits in the signal path - ADC - data-converter - mixed-signal IC family, providing the bridge between analog front-ends (LNAs, filters, drivers) and a downstream DSP, FPGA, or microcontroller. Key specifications include a flexible 1 Vp-p to 2 Vp-p input range, 575 MHz full-power input bandwidth, ±1 LSB (typical) integral non-linearity, ±0.5 LSB differential non-linearity, and an integrated sample-and-hold amplifier with a clock-duty-cycle stabilizer. Power consumption is typically 75 mW at 25 Msps from a single 3V supply, and shutdown/nap modes reduce dissipation further for power-sensitive designs. The 32-pin TQFP-32 (5x5 mm) plastic package supports surface-mount assembly and is pin-compatible with the broader LTC2246/47/48 family. Applications include high-end imaging, communications transceivers, instrumentation, and any signal chain that needs 14-bit dynamic range at moderate sampling rates. The wide input bandwidth allows undersampling of IF signals in communications systems. When designing with this part, ensure the analog input is properly driven by a differential amplifier or transformer, and decouple AVDD and OVDD pins separately. The clock-duty-cycle stabilizer relaxes clock-source requirements, but jitter still directly impacts SNR - use a low-jitter oscillator. This page synthesizes distributor pricing, application examples, and pin-compatible family members that go beyond the datasheet's typical-application circuit.
LTC2246HLX - 14-Bit 25Msps Low Power 3V ADC | Analog Devices
The Analog Devices LTC2246HLX is a 14-bit, 25Msps low-power 3V analog-to-digital converter housed in a 48-pin LQFP (7mm x 7mm) package, designed for digitizing high-frequency, wide-dynamic-range signals. The part is part of the LTC2246H automotive-temperature-grade family (H-suffix, -40C to +125C operation) and the LX suffix denotes tape-and-reel packaging. According to the LTC2246H datasheet, the converter delivers 74.5 dB SNR and 90 dB SFDR at 25Msps with 1V P-P to 2V P-P flexible input range, 575MHz full-power bandwidth sample-and-hold, and shutdown/nap power-down modes. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes for downstream digital signal processing. ADCs sit in the signal chain between analog front-ends (amplifiers, filters, mixers) and digital processors (FPGAs, DSPs, microcontrollers). Within the converter family, the LTC2246HLX uses a pipelined multi-stage architecture that delivers high sample rates at moderate resolution (14-bit) with low power consumption, making it a member of the high-speed-ADC class. Pipelined ADCs trade latency for throughput, ideally suited to streaming applications such as imaging and communications. Key features include ±1LSB INL (typical), ±0.5LSB DNL (typical), no missing codes over the full automotive temperature range, and 1LSB transition noise. The part operates from a single 3V supply and supports a clock-duty-cycle stabilizer to ease timing-source constraints. It is pin-compatible with the 12-bit LTC2226H, allowing system designers to migrate between resolution grades without PCB rework. According to the LTC2246H datasheet, the device achieves 75 dB SNR and 90 dB SFDR for demanding communications signal chains. The pipelined architecture uses multiple low-resolution flash stages with inter-stage residue amplification and digital error correction, achieving high sampling rates with low latency compared to successive-approximation (SAR) ADCs of similar resolution. The flexible 1V P-P to 2V P-P input range (selectable via internal PGA) and 575MHz input bandwidth allow the part to directly digitize IF signals in communications receivers or high-impedance sensor outputs in imaging systems. Single-ended or differential analog inputs are supported. Typical applications include portable and benchtop ultrasound imaging front-ends, communications receivers (IF sampling, software-defined radio), industrial non-destructive test (NDT) equipment, automotive driver-assistance sensors, and high-speed data acquisition cards for instrumentation. The automotive temperature grade (-40C to +125C) makes the LTC2246HLX particularly suited to in-cabin and chassis-mounted electronics. When designing with this part, provide a low-jitter clock source (typically < 1ps RMS) to preserve SNR at high input frequencies, and route analog and digital grounds with separate planes joined under the ADC. The shutdown and nap modes enable significant power savings in pulsed or duty-cycled applications, reducing dissipation from the typical 75mW to under 1mW in shutdown. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2249IUH - 14-Bit 80Msps Low Power ADC | Analog Devices
The Analog Devices LTC2249IUH is a 14-bit, 80Msps, low-power 3V analog-to-digital converter (ADC) housed in a 32-pin QFN (5x5) exposed-pad package, designed for digitizing high-frequency, wide-dynamic-range signals. The device delivers 73dB SNR and 90dB SFDR at a 70MHz input, with typical INL of ±1LSB and DNL of ±0.5LSB, guaranteeing no missing codes across the full operating range. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sampling rate. ADCs sit at the boundary between the analog front-end (sensors, amplifiers, filters) and the digital back-end (FPGAs, DSPs, microcontrollers) in a signal chain, and their sampling rate, resolution, and dynamic range determine the usable bandwidth and fidelity of the entire system. The LTC2249IUH occupies the high-speed, mid-resolution tier of this taxonomy: ADC > pipelined ADC > 14-bit 80Msps ADC > power management/data conversion mixed-signal IC > semiconductor. Key features include a flexible differential input range of 1V to 2V peak-to-peak, a 575MHz full-power analog input bandwidth, optional internal dither for improved low-amplitude linearity, and a single 3V supply (2.85V to 3.4V). Power consumption is 222mW at 80Msps, and the part offers a shutdown/nap mode that drops quiescent current to microampere levels for power-cycled applications. The 32-lead QFN package with an exposed die-attach pad provides a low thermal resistance path for the internal 222mW dissipation. The LTC2249 uses a pipelined multi-stage switched-capacitor architecture with digital output error correction, which is the standard topology for 14-bit 80Msps converters and which allows the high sample rate without the latency of a successive-approximation register (SAR) architecture. The 14-bit parallel CMOS/TTL-compatible output bus and the on-chip sample-and-hold eliminate the need for an external track-and-hold amplifier in most applications. Typical applications include cellular basestation receivers, medical imaging front-ends (ultrasound, digital x-ray), cable-headend DOCSIS downstream digitizers, and high-end test-and-measurement instrumentation. The combination of wide input bandwidth, dither, and high SFDR makes the part well suited to undersampling IF signals in software-defined radio (SDR) and communications receivers. When designing with the LTC2249IUH, pay attention to the analog input network: the device expects a 50-ohm-terminated differential drive, and a transformer (e.g., ADT1-1WT) or a high-speed differential op-amp (e.g., AD8138) is typically used to convert single-ended signals to the required differential form. Use a solid ground plane under the exposed pad (EP) and stitch vias around the perimeter to manage the 222mW dissipation and to keep the digital return currents from coupling into the analog inputs. This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the LTC22xx family, and practical design notes not found in the manufacturer datasheet alone, providing a single reference for component selection, PCB layout, and signal-chain design.
LTC2256CUJ-12 - 12-Bit 25Msps Ultralow Power 1.8V ADC | Analog Devices
The Analog Devices LTC2256CUJ-12 is a 12-bit, 25 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic-range signals in a 40-lead QFN (6 mm x 6 mm) package with exposed pad. It integrates a single differential input, an internal sample-and-hold, and a precision reference, achieving 71.1 dB SNR and 88 dB spurious-free dynamic range (SFDR) at the Nyquist frequency while consuming only 62 mW from a single 1.8 V analog supply. What is an SAR/pipelined ADC? An analog-to-digital converter (ADC) translates continuous analog signals into discrete digital codes. The pipelined ADC architecture, used in the LTC2256CUJ-12, combines multiple low-resolution flash stages with digital error correction to deliver high sampling rates (tens to hundreds of MSPS) at moderate resolution (10-16 bit), suiting it to wideband communications, imaging, and instrumentation. Within the broader semiconductor hierarchy, the LTC2256CUJ-12 belongs to the data-converter family (ADC), which sits under mixed-signal ICs and interface ICs. Key specifications include 0.17 ps RMS ultralow jitter for accurate IF undersampling, ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical) with no missing codes over temperature, and 0.3 LSB RMS transition noise. The digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, with a separate output supply pin allowing the CMOS swing to range from 0.5 V to 1.8 V. The 1.8 V single-supply operation makes it well-suited to low-power, battery-friendly designs. The architecture combines a front-end differential S/H, a multi-stage pipelined quantizer chain, and an internal bandgap reference, while supporting an optional external reference for noise-critical paths. AC performance - 71.1 dB SNR and 88 dB SFDR at 25 Msps - is preserved across input frequencies up to and beyond Nyquist, with sub-picosecond aperture jitter enabling accurate undersampling of IF signals commonly used in communications and radar systems. Typical applications include cellular base-station receivers, IF digitizers in software-defined radio (SDR), medical imaging front-ends, handheld portable test equipment, and low-power instrumentation. The combination of 1.8 V single-supply operation, 25 Msps speed, and differential input makes it ideal for any signal chain where wide dynamic range and low power must coexist. When designing in this part, use a multilayer PCB with a continuous unbroken ground plane and place the exposed pad on a thermal/ground copper pour. Decouple AVDD, DVDD, and OVDD with 10 uF and 0.1 uF ceramic capacitors placed as close to the pins as possible, and route differential analog inputs with matched impedance and length to preserve the rated SFDR. A separate OVDD supply lets you interface directly to 1.8 V logic without level shifters. This page consolidates distributor stock, verified pin-compatible alternatives, and application guidance that goes beyond the manufacturer's datasheet so procurement and design engineers can decide quickly whether the LTC2256CUJ-12 fits their signal chain.
LTC2256CUJ-14 - 14-Bit 25Msps Ultralow Power 1.8V ADC | ADI
The Analog Devices LTC2256CUJ-14 is a 14-bit, 25 Msps, ultra-low-power pipelined analog-to-digital converter (ADC) that operates from a single 1.8V supply and dissipates only 35 mW at full sample rate, housed in a compact 40-pin 6 mm x 6 mm QFN (UJ suffix) package. According to the Analog Devices datasheet, it offers 73 dB SNR, ±1 LSB INL (typical), ±0.3 LSB DNL (typical), and no missing codes over temperature, with transition noise of just 1.13 LSB RMS. The digital outputs are software-configurable as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, while a separate output supply lets the CMOS swing be set from 1.2V to 1.8V for direct interface to modern FPGAs and ASICs. A pipelined ADC is a multi-stage converter that samples an analog input and distributes the conversion work across successive low-resolution flash stages; this architecture enables high sample rates with low power consumption, making pipelined ADCs the standard for communications, imaging, and instrumentation front ends. As part of the broader ADC hierarchy, pipelined converters sit between successive-approximation register (SAR) ADCs and flash ADCs in the speed/power trade-off curve, and the LTC2256 family specifically targets applications where both low power (35 mW at 25 Msps) and high dynamic range are required. Key features of the LTC2256-14 include 800 MHz full-power input bandwidth, a flexible 1V to 2V peak-to-peak differential input range, optional internal S/H, optional data output randomizer for EMI suppression, and an optional clock duty-cycle stabilizer that relaxes clock-source requirements. The integrated SPI port allows per-channel configuration, gain/offset calibration, and output-mode selection without external hardware. Nap and full shutdown modes drop consumption to microampere levels, making this ADC well-suited for battery-powered and power-cycled systems. Typical applications include handheld and portable test instrumentation, ultrasound front ends, low-power software-defined radio (SDR), CCD imaging, and broadband communications IF sampling. The pin-compatible LTC2257-14 (40 Msps) and LTC2258-14 (65 Msps) siblings let designers scale performance without PCB rework, and the LTC2256-12 version drops resolution to 12-bit for cost-sensitive designs. When designing with the LTC2256CUJ-14, drive the inputs differentially with a low-jitter clock source to extract full SNR, and provide a low-noise 1.8V LDO (e.g., an ultralow-noise LDO with at least 75 dB PSRR at the ADC's Nyquist frequency) on the analog supply. Decouple AVCC with 10 µF/0.1 µF pairs close to the pins and route the digital outputs away from the analog inputs to preserve 73 dB SNR. This page synthesizes distributor pricing, drop-in alternatives, and practical layout notes not found in the manufacturer datasheet alone.