ADC/DAC
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LTC2256IUJ-12 - 12-Bit 25 MSPS Ultra-Low Power ADC | Analog Devices
The Analog Devices LTC2256IUJ-12 is a 12-bit, 25 MSPS pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6 mm x 6 mm x 0.75 mm with exposed pad) package. It combines 12-bit resolution, 25 MSPS sampling, and a 1.8 V single analog supply with ultra-low power consumption optimized for portable, communications, and instrumentation designs. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The LTC2256IUJ-12 belongs to the pipelined ADC sub-family, which uses a multi-stage switched-capacitor architecture to achieve high sampling rates (tens of MSPS) while keeping per-stage power dissipation modest. Within the broader taxonomy, this device is a successive-approximation/pipelined hybrid low-power ADC, classified under data converters -> ADC -> high-speed pipelined ADC -> mixed-signal IC -> semiconductor. Pipelined ADCs are the workhorse of communication baseband, IF sampling, and imaging front-ends because they balance speed, resolution, and power efficiency better than flash or SAR alternatives in the 8- to 16-bit, 20-200 MSPS range. Key features include ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), no missing codes over temperature, and 0.3 LSB RMS transition noise. The digital outputs are software-configurable: full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, allowing the same part to interface with FPGAs, ASICs, or standard microprocessors. A separate output power supply pin (OVDD) lets the CMOS output swing range from 1.2 V to 1.8 V, simplifying level translation to 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V host logic without external level shifters. Architecturally, the LTC2256IUJ-12 uses a multi-bit-per-stage pipelined front-end followed by digital error correction, which both reduces the number of required sample-and-hold amplifier stages and improves linearity. The integrated input buffer accepts differential or single-ended drive, and the integrated reference can be bypassed for an external reference in precision applications. The 40-QFN exposed-pad package provides a low thermal resistance path, enabling operation across the -40 °C to +85 °C industrial temperature range without forced-air cooling. Typical applications include communications IF/baseband sampling, portable instrumentation, ultrasound and medical imaging front-ends, and low-power multi-channel data acquisition systems. Its 1.8 V analog supply and configurable output swings make it especially well suited to battery-powered or FPGA-co-designed platforms. When designing with this ADC, observe the datasheet-recommended input common-mode voltage, drive the clock with a low-jitter source, and provide a clean 1.8 V LDO upstream to preserve SNR. Decouple AVDD with 10 µF + 0.1 µF capacitors placed as close to the supply pins as possible, and tie the exposed pad to a solid ground plane for thermal dissipation. This page synthesizes distributor pricing, drop-in alternatives from the same ADI pin-compatible family, and practical design notes not found in the manufacturer datasheet.
LTC2257CUJ-12 - 12-Bit 40Msps Ultralow Power 1.8V ADC | Analog Devices
The Analog Devices LTC2257CUJ-12 is a 12-bit, 40 Msps pipelined analog-to-digital converter that operates from a single 1.8V supply and dissipates only 79 mW, housed in a 40-pin QFN (6 mm x 6 mm) package. It accepts single-ended analog inputs with selectable 1V P-P to 2V P-P full-scale ranges, plumbed into a sample-and-hold front end with 800 MHz full-power input bandwidth. The digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, and a separate output supply rail lets the CMOS swing range from 1.2V to 1.8V to match downstream FPGA or ASIC I/O. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog voltage into a discrete-time, discrete-amplitude digital code. Pipelined ADCs in particular use a cascade of low-resolution stages to achieve high sample rates with low power, and they sit inside the broader data-converter hierarchy as the dominant architecture for sample rates from ~10 Msps to ~250 Msps at resolutions of 8 to 16 bits. The LTC2257 family is a pin-compatible family of 14-bit and 12-bit converters spanning 65, 40, and 25 Msps grades. Key electrical specifications include ±0.3 LSB typical integral non-linearity (INL), ±0.1 LSB typical differential non-linearity (DNL), no missing codes over the full -40C to +85C operating range, and 0.3 LSB RMS transition noise. An optional data output randomizer suppresses digital switching noise on the output bus, and an optional clock duty cycle stabilizer relaxes the jitter requirement on the external encode clock. The architecture is a multi-bit-per-stage pipelined core with on-chip reference, front-end sample-and-hold, and digital error correction. SPI-configurable modes let the user trade noise, power, and output format at runtime, and shutdown plus nap modes cut quiescent draw for battery-powered or duty-cycled systems. Typical applications include portable and battery-powered instrumentation, ultrasound front-end signal chains, low-cost digital oscilloscopes, IF sampling for software-defined radio, and industrial data acquisition boards. The combination of 40 Msps throughput, 79 mW dissipation, and flexible LVDS/CMOS output makes it well suited for designs where board power and connector pin count are constrained. When designing with this part, drive the encode input with a low-jitter CMOS clock and keep analog input traces matched and short to preserve the 800 MHz input bandwidth. A separate output supply pin lets you connect 1.8V logic directly without level shifters, but you must still provide clean decoupling on both the analog and output rails. This page synthesizes distributor pricing, drop-in alternatives from the same Analog Devices LTC225x and LTC224x families, and practical design notes not found in the bare datasheet summary, providing a one-stop reference for evaluation, sourcing, and second-source risk planning.
LTC2257CUJ-14 - 14-Bit 40Msps Ultralow Power ADC | Analog Devices
The Analog Devices LTC2257CUJ-14 is a 14-bit, 40 Msps ultralow-power pipeline analog-to-digital converter (ADC) that operates from a single 1.8V supply and dissipates only 49 mW at full speed, housed in a 40-pin 6 mm × 6 mm QFN package. It supports selectable input ranges of 1 Vp-p to 2 Vp-p with a 800 MHz full-power sample-and-hold bandwidth, and provides DC accuracy of ±1 LSB INL (typical) and ±0.3 LSB DNL (typical) with no missing codes over the commercial temperature range. An ADC (analog-to-digital converter) is an integrated circuit that samples continuous analog signals and converts them to discrete digital codes, bridging the analog and digital domains in mixed-signal systems. Pipeline ADCs such as the LTC2257 are a high-throughput class that use a cascaded multi-stage architecture (typically 1.5-bit-per-stage plus a final flash) to achieve sample rates from tens of MHz to over 100 MHz while keeping per-stage resolution low and power consumption modest. They fit between successive-approximation (SAR) ADCs, which sample under ~5 Msps, and high-speed flash ADCs, which trade power for the highest rates. Pipeline ADCs sit within the broader data-converter hierarchy, themselves part of the mixed-signal/power-management fabric of an SoC or FPGA-based system. Key features of the LTC2257-14 include a transition noise floor of 1.13 LSB RMS, flexible digital outputs (full-rate CMOS, double-data-rate CMOS, or DDR LVDS) selectable per design, an output supply domain from 1.2V to 1.8V for glueless logic interfacing, optional data output randomizer and clock duty-cycle stabilizer for EMI/clock-jitter tolerance, plus shutdown and nap modes for power-sensitive handheld or battery-backed designs. Configuration is through a serial SPI port. The pin-compatible 14-bit/12-bit family (LTC2257-14, LTC2257-12, LTC2256-14 at 25 Msps, LTC2258 family at 65 Msps) shares the same 40-pin QFN (6 × 6) footprint, letting designers scale sample rate or resolution without re-laying out the PCB. This combination of low power, flexible output interface, and pin-compatible siblings makes the LTC2257-14 a strong fit for portable imaging, ultrasonic, communications, and industrial instrumentation front ends. Typical applications include handheld oscilloscopes and spectrum analyzers, medical ultrasound receivers, multi-standard software-defined radio receivers, image scanners, and low-power industrial process-control data acquisition boards. The 49 mW dissipation also suits remote or solar-powered instrumentation. When designing with the LTC2257-14, place the input network and reference decoupling close to the pins, use a low-jitter clock, and follow the recommended PCB layout for the exposed pad to keep junction temperature low. The pin-compatible family lets a designer migrate to a higher or lower sample rate by changing only the part number.
LTC2257IUJ-14 - 14-bit, 40Msps Ultralow Power 1.8V ADC | Analog Devices
The Analog Devices LTC2257IUJ-14 is a 14-bit, 40 Msps pipelined analog-to-digital converter (ADC) with ultralow power architecture, housed in a 40-pin QFN (6x6 mm) package. It operates from a 1.8V analog supply and a separate 1.2V to 1.8V digital supply for flexible CMOS/LVDS interface levels, with a maximum power consumption of approximately 49 mW at 40 Msps. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC design that processes analog input samples through multiple cascaded low-resolution flash stages, achieving sample rates from tens to hundreds of Msps while maintaining 12- to 16-bit resolution. Within the broader ADC taxonomy, it sits between flash ADCs (fastest, lowest resolution) and sigma-delta ADCs (slowest, highest resolution), making it the dominant architecture for communications infrastructure, IF digitisation, and high-speed instrumentation. Key features of the LTC2257IUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and 1.13 LSB RMS transition noise. The digital outputs are configurable as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS. Integrated functions include an optional clock duty-cycle stabilizer, shutdown and nap modes for power savings, and a serial SPI port for configuration. The device is part of a pin-compatible family that includes 12-bit and 14-bit versions at 25/40/65 Msps (LTC2256-14, LTC2257-14, LTC2258-14), enabling system designers to scale performance without layout changes and the same architecture down to lower power budgets. Typical applications include communications infrastructure (cellular basestation IF digitisation, microwave links), high-speed imaging, portable test and measurement, and ultrasonics. The 1.8V core supply and 49 mW dissipation allow battery-powered designs without sacrificing dynamic range. When designing with this ADC, prioritise the analog input front-end (driver amplifier, antialias filter), supply decoupling, and PCB layout symmetry around the differential analog inputs. Use the exposed pad for thermal and ground-plane stitching. This page synthesises distributor pricing, drop-in pin-compatible alternatives, and design notes beyond what is found on the manufacturer product page, giving engineers a single source for procurement and substitution analysis.
LTC2258CUJ-12 - 12-Bit 65Msps 1.8V Ultra-Low Power ADC | ADI
The Analog Devices LTC2258CUJ-12 is a 12-bit, 65 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic-range signals with ultra-low power consumption from a single 1.8V supply. Housed in a 40-lead QFN (6 mm × 6 mm) package, it integrates pin-compatible 12-bit and 14-bit versions of the same architecture, simplifying board-level migration across precision, speed, and resolution variants. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog input voltage and converts each sample into a discrete digital code. Pipelined ADCs such as the LTC2258-12 use multiple low-resolution stages to achieve high sample rates at moderate power, placing them in the converter hierarchy between successive-approximation (SAR) ADCs and flash ADCs. They are widely used in communications, instrumentation, and defense systems where gigahertz-class analog front-ends must be digitized accurately. Key specifications include 71.1 dB SNR and 88 dB spurious-free dynamic range (SFDR) for AC applications, 0.3 LSB RMS transition noise, ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical), with no missing codes over the full operating temperature range. Ultralow 0.17 ps RMS aperture jitter enables excellent undersampling of IF frequencies. Selectable digital outputs include full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, while a separate output supply rail lets the CMOS swing range from 1.2V to 1.8V for flexible logic-level interfacing. The converter features an optional clock duty-cycle stabilizer, shutdown and nap modes for power-sensitive applications, and a serial SPI port for mode configuration. The 40-pin 6×6 mm QFN package provides a compact footprint with excellent thermal performance, while the single 1.8V supply dramatically simplifies system power-tree design for portable, battery-powered, and high-density designs. Typical applications include cellular base-station receivers, IF sampling for software-defined radios, digital oscilloscopes, spectrum analyzers, medical imaging front-ends, and high-speed data acquisition cards. The combination of 71.1 dB SNR, 88 dB SFDR, and 0.17 ps RMS jitter makes the part particularly suitable for undersampling architectures in communications receivers. When designing with this ADC, ensure the analog input is driven by a low-noise, low-distortion differential amplifier with bandwidth well above the Nyquist frequency, and that the clock source provides <0.5 ps RMS jitter to preserve SNR. Use a low-inductance ground plane and keep analog/digital domains partitioned to avoid digital coupling into the analog inputs. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB/clock design notes that are not aggregated in the manufacturer datasheet.
LTC2258CUJ-14 - 14-Bit, 65Msps Ultralow Power 1.8V ADC | ADI
The Analog Devices LTC2258CUJ-14 is a 14-bit, 65 Msps pipelined analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals with ultralow power consumption from a single 1.8V supply. It is housed in a 40-lead (6mm x 6mm) QFN package (UJ suffix) and integrates a front-end PGA plus a high-performance pipeline core. The part targets applications such as handheld and battery-powered instruments, communications imaging, portable ultrasound, and low-power instrumentation. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a defined sample rate. In the broader hierarchy, the LTC2258CUJ-14 sits within successive-approximation/pipelined ADCs -> data converters -> signal chain ICs -> mixed-signal semiconductors. Pipelined ADCs like this one are optimized for high sample rates (tens of Msps and above) where SAR converters would consume more energy per conversion. The LTC2258 family specifically targets the 14-bit, 25-65 Msps segment with sub-100 mW power dissipation. Key features include ±1 LSB INL (typical), ±0.3 LSB DNL (typical) and no missing codes over temperature, with 1.13 LSB RMS transition noise. The digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, and a separate output supply rail allows the CMOS swing to range from 1.2V to 1.8V for flexible host interface compatibility. According to the manufacturer datasheet, the family also integrates an SPI configuration port plus shutdown and nap power-saving modes, with optional clock duty cycle stabilization. Architecturally, the device pairs a switched-capacitor input network with a multi-stage pipelined quantizer and on-chip reference. The ultralow power dissipation is achieved through a 1.8V core supply and aggressive clock gating during nap and shutdown modes. The integrated PGA simplifies front-end design by allowing direct coupling of single-ended or differential signals without an external driver op-amp in many cases. Typical applications include communications baseband and IF sampling, handheld spectrum analyzers, medical imaging (including portable ultrasound front ends), and industrial data acquisition front ends. When designing with this part, attention should be paid to analog input common-mode voltage, LVDS/CMOS output bus routing, and the recommended decoupling network to achieve the datasheet SNR/SFDR performance. A separate output supply pin allows the CMOS logic swing to be matched to the host ASIC/FPGA I/O voltage without level shifters. This page synthesizes distributor pricing, same-package pin-compatible variants, application pairing guidance, and PCB/design notes not found in the bare datasheet, allowing engineers to compare drop-in alternatives and second-source the LTC2258CUJ-14 in volume production.
LTC2258IUJ-12 - 12-Bit 65Msps Ultralow Power ADC | Analog Devices
The Analog Devices LTC2258IUJ-12 is a 12-bit, 65 msps, single-channel pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6 mm x 6 mm) package with an exposed pad. It is optimized for digitizing high-frequency, wide-dynamic-range signals with 1.8 V analog and digital supplies, ultralow power dissipation, and selectable CMOS or LVDS digital interfaces. An analog-to-digital converter (ADC) is a semiconductor device that converts continuous analog signals into discrete digital codes, enabling downstream processing by microcontrollers, DSPs, or FPGAs. Pipelined ADCs such as the LTC2258IUJ-12 use a multi-step sample-and-hold and sub-ADC architecture to achieve sampling rates from 25 msps to over 1 msps while maintaining low power consumption. Within the broader signal-chain hierarchy, the ADC sits between the analog sensor or amplifier stage and the digital processor, and its dynamic range, SNR, and SFDR directly set system-level performance in communications, imaging, and instrumentation applications. Key specifications include 71.1 dB SNR and 88 dB spurious-free dynamic range (SFDR) at 65 msps input frequency, 0.3 LSB INL (typical) and 0.1 LSB DNL (typical) with no missing codes over temperature, and 0.3 LSB RMS transition noise. The digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, while a separate output power supply allows the CMOS output swing to range from 1.2 V to 1.8 V for direct interface to modern ASICs and FPGAs. The pipelined architecture samples input signals above 70 MHz while the ultralow-power 1.8 V operation minimizes thermal dissipation, enabling compact layouts without aggressive thermal management. Programmable operating modes are accessible through either a parallel interface or a more flexible serial interface. The exposed-pad 40-lead QFN package keeps the device footprint at 36 mm^2 while providing a low thermal-resistance path. Typical applications include cellular base-station receivers, IF-sampling software-defined radios, portable imaging systems, and low-power instrumentation. The wide LVDS/CMOS output flexibility and low-power 1.8 V operation make it well suited to battery-powered and densely populated boards. When designing with this device, place input capacitors directly at the analog input pins and route output clocks with controlled impedance to minimize coupling into the analog input. A clean unbroken ground plane is recommended, and a multilayer PCB with an internal ground plane is preferred to preserve AC performance. This page synthesizes distributor pricing, same-family drop-in alternatives from the LTC2257-12 and LTC2256-12 families, and practical PCB design notes that complement the manufacturer datasheet and typical application circuit.
LTC2258IUJ-14 - 14-Bit 65Msps Ultralow Power 1.8V ADC | Analog Devices
The Analog Devices LTC2258IUJ-14 is a 14-bit, 65 Msps pipelined analog-to-digital converter (ADC) that targets ultralow-power, high-dynamic-range signal acquisition. Per the manufacturer datasheet, the device delivers 74 dB SNR and 88 dB SFDR at a 65 Msps sampling rate, consumes only 81 mW from a single 1.8 V supply, and offers pin-selectable output modes including full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS, with the CMOS output swing independently set between 1.2 V and 1.8 V via a separate output supply pin. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed Nyquist ADC architecture that uses cascaded low-resolution flash stages to digitize an analog input; each stage resolves a few bits then drives a residue amplifier for the next stage, enabling tens to hundreds of Msps throughput with 10-16 bit resolution and excellent power efficiency for communications, imaging, and instrumentation front-ends. This category sits hierarchically under analog-to-digital converter -> data converter -> mixed-signal IC -> semiconductor. Key differentiating specifications include an integrated track-and-hold with 800 MHz full-power bandwidth, an input range selectable from 1 Vp-p to 2 Vp-p for direct coupling to IF/RF or baseband signal chains, 1.13 LSB RMS transition noise, and no-missing-codes behavior over the full industrial temperature range. DC linearity is robust at +/-1 LSB INL (typical) and +/-0.3 LSB DNL (typical). The LTC2258IUJ-14's architecture combines a high-bandwidth front-end S/H with multi-stage pipeline conversion and a flexible digital output block; an optional on-chip clock duty-cycle stabilizer relaxes the jitter sensitivity of upstream clock sources, and an optional data-output randomizer reduces digital pattern-dependent interference on the PCB. The IUJ-14 grade is the industrial-temperature (-40 C to +85 C) variant in a 6 mm x 6 mm QFN-40 (UJ) package with an exposed pad. Typical applications span portable and battery-powered digital oscilloscopes and handheld instrumentation, software-defined radio (SDR) and broadband communications IF digitization, industrial imaging and machine-vision front-ends, ultrasound receive channels, and high-speed data-acquisition cards. Pin compatibility with the 12-bit LTC2258IUJ-12, 40 Msps LTC2257IUJ-14, and 25 Msps LTC2256IUJ-14 in the same QFN-40 package allows designers to swap resolution/speed without re-laying out the board. Design tip: keep analog and digital grounds separated by a split ground plane joined beneath the exposed pad, and place a 0.1 uF plus 10 uF decoupling pair as close as possible to both the 1.8 V AVDD pin and the separate OVDD pin to preserve SNR at high input frequencies. This page synthesizes the datasheet, octopart pricing tiers, and same-footprint drop-in alternatives in the LTC2256/57/58 family - practical engineering context that is not found on a manufacturer product page alone.
LTC2260CUJ-14 - 14-Bit 105Msps Ultra-Low Power 1.8V ADC | Analog Devices
The Analog Devices LTC2260CUJ-14 is a 14-bit, 105 Msps ultra-low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6 mm × 6 mm) package with an exposed pad. It operates from a single 1.8 V analog supply and consumes approximately 130 mW of power at full 105 Msps sampling rate. The device features an optional clock duty cycle stabilizer, shutdown and nap modes, and a serial SPI port for configuration of output mode, gain, and power-down behavior. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog input voltages into discrete digital output codes at a defined sampling rate. Pipelined ADCs use multiple cascaded low-resolution stages to achieve high sampling rates at moderate resolution; they sit within the hierarchy: ADC → data converter → mixed-signal IC → semiconductor. The LTC2260 family occupies the high-speed, low-power end of this taxonomy, designed for portable and thermally constrained systems where a 1.8 V supply rail is already present. Key features of the LTC2260CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical) with no missing codes over temperature, and a low 1.2 LSB RMS transition noise. The flexible digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, and a separate output power supply allows the CMOS output swing to range from 1.2 V to 1.8 V. Pin-compatible 14-bit and 12-bit versions enable resolution scaling within the same PCB footprint. Architecturally, the device uses a multi-stage pipelined switched-capacitor core followed by a digital error-correction block, with an internal bandgap reference and integrated input common-mode buffer. An optional duty-cycle stabilizer corrects for clock asymmetry, allowing the use of low-cost CMOS oscillators without degrading AC performance. The exposed thermal pad provides a low-resistance thermal path, critical at sustained 105 Msps operation in compact layouts. Typical applications include portable and battery-powered imaging systems, ultrasound front-end signal chains, software-defined radio receivers, low-cost digital oscilloscopes, and industrial multi-channel data acquisition boards. Designers favor the LTC2260CUJ-14 when 14-bit resolution and >100 Msps throughput are required without exceeding the thermal or power budget of a fanless enclosure. When designing with this ADC, place decoupling capacitors as close as possible to each supply pin and stitch the exposed pad with a continuous ground plane to achieve specified SNR. Consider activating the duty-cycle stabilizer when sourcing the sample clock from a non-50% source, and use LVDS output mode for >80 MHz parallel interfaces to reduce EMI and ground bounce. This page synthesizes distributor pricing, same-package drop-in alternatives from Analog Devices and competitor equivalents, and practical design notes not found on the manufacturer datasheet cover page.
LTC2260IUJ-12 - 12-Bit 105Msps 1.8V ADC | Analog Devices
The Analog Devices LTC2260IUJ-12 is a 12-bit, 105 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin 6mm x 6mm QFN package. It operates from a single 1.8V supply, dissipating only 124 mW at full sample rate, and supports selectable full-scale input ranges from 1 Vp-p to 2 Vp-p. Per the Analog Devices datasheet, the DC specifications include ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), no missing codes over temperature, and a low 0.3 LSBRMS transition noise. What is a pipelined ADC? A pipelined ADC is a multi-stage analog-to-digital converter architecture that processes the input sample through cascaded low-resolution flash stages, achieving high sampling rates while keeping per-stage complexity manageable. Within the broader signal-chain taxonomy, the LTC2260IUJ-12 belongs to the family of high-speed, low-power SAR/pipeline converters used between the analog front end and a digital signal processor, FPGA, or ASIC. Pipelined ADCs sit alongside successive-approximation (SAR) and flash ADCs as the dominant architectures for sampling rates from a few Msps to several hundred Msps. Key features of the LTC2260IUJ-12 include single 1.8V supply operation, selectable CMOS, double-data-rate CMOS, or double-data-rate LVDS outputs, an 800 MHz full-power sample-and-hold bandwidth, and a separate output supply that allows the CMOS swing to range from 1.2 V to 1.8 V. Optional features include a data output randomizer, clock duty cycle stabilizer, shutdown and nap modes, and an SPI serial port for configuration. The #PBF suffix indicates a lead-free, RoHS-compliant finish. The LTC2260IUJ-12 is pin-compatible with the 14-bit LTC2260-14 and 12-bit LTC2261-12/LTC2259-12 siblings in the same 40-QFN footprint, simplifying board reuse when system requirements change resolution or sample rate. The pipelined architecture combined with internal reference and selectable clock options reduces external component count and eases timing closure with downstream FPGAs. Typical applications include high-bandwidth communications receivers, portable instrumentation, digital oscilloscopes, ultrasound imaging front-ends, and software-defined radio digitizers where low power consumption and high spurious-free dynamic range are required. When designing the analog input network, ensure the input is AC-coupled or DC-biased within the selected full-scale input range, and route the encode clock with controlled impedance to preserve aperture jitter performance. Use the optional LVDS mode when interfacing to modern FPGAs with LVDS-capable deserialization blocks to minimize switching noise on the digital supply rail.
LTC2260IUJ-14 - 14-Bit 105Msps Ultralow Power 1.8V ADC | ADI
The Analog Devices LTC2260IUJ-14 is a 14-bit, 105 Msps ultralow-power pipelined analog-to-digital converter (ADC) with one input channel, housed in a 40-pin 6 mm × 6 mm QFN package. The device operates from a single 1.8 V supply and typically consumes 106 mW at 105 Msps, while DC performance includes ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and a low 1.2 LSB RMS transition noise. Digital outputs can be configured as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, and a separate output supply lets the CMOS swing range from 1.2 V to 1.8 V for direct interface to modern FPGAs and ASICs. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and converts them into discrete digital codes for processing by microcontrollers, DSPs, FPGAs, or software. Within the broader signal chain, the ADC sits between the analog front end (amplifiers, filters, drivers) and the digital back end. Pipelined ADCs like the LTC2260-14 use a multi-stage architecture to achieve high sample rates at moderate resolution while keeping per-stage comparator counts and power dissipation low, making them well suited for high-speed data acquisition, communications, and imaging. Key features of the LTC2260IUJ-14 include an 800 MHz full-power bandwidth sample-and-hold, selectable input ranges from 1 V P-P to 2 V P-P, an optional data output randomizer to reduce switching spurs, an optional clock duty cycle stabilizer, plus shutdown and nap modes for power management. The serial SPI port allows configuration of output mode, input range, and power-down behavior without external hardware changes. Architecture-wise, the part is pin-compatible with the 12-bit LTC2260-12 and with the higher/lower-speed LTC2261-14 (125 Msps) and LTC2259-14 (80 Msps) variants, simplifying platform design across resolutions. The ultralow 106 mW dissipation makes it useful for thermally constrained embedded systems and portable instruments. Typical applications include communications baseband receivers, high-speed imaging and instrumentation, software-defined radios, portable test and measurement, and medical ultrasound front-end boards where 14-bit dynamic range and 105 Msps sample rate offer a strong speed/resolution/power balance. When designing with this ADC, ensure the analog inputs are driven by a low-noise, low-distortion amplifier capable of settling within one aperture window, and keep the analog/digital ground returns separate to limit coupling. Decouple the analog supply with low-ESR ceramic capacitors close to the AVDD pins to preserve SFDR. This page synthesizes distributor pricing, parametric drop-in alternatives within the same QFN-40 (6x6) family, and practical design notes that are not consolidated in the manufacturer datasheet alone.
LTC2261CUJ-12 - 12-Bit 125Msps Ultra-Low-Power ADC | Analog Devices
The Analog Devices LTC2261CUJ-12#PBF is a 12-bit, 125 Msps pipelined analog-to-digital converter (ADC) optimized for digitizing wide dynamic range, high-frequency signals in demanding communications applications. Packaged in a 40-pin QFN (6 mm x 6 mm) with exposed pad, the part delivers 70.8 dB SNR and 85 dB spurious-free dynamic range (SFDR) while consuming only 124 mW from a single 1.8 V supply. The ADC also provides an 800 MHz full-power sample-and-hold bandwidth. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a defined sampling rate. The pipelined ADC architecture uses multiple low-resolution stages to achieve high throughput with low latency, and it occupies the middle ground between successive-approximation (SAR) converters (low speed, low power) and flash converters (very high speed, high power). In the broader taxonomy, the LTC2261CUJ-12 belongs to the high-speed pipelined ADC > data converter > signal-chain IC > mixed-signal semiconductor hierarchy. Key features of the LTC2261CUJ-12 include selectable input ranges of 1 Vp-p to 2 Vp-p, CMOS, DDR CMOS or DDR LVDS output modes, an optional data output randomizer, an optional clock duty-cycle stabilizer, shutdown and nap power-down modes, and a serial SPI port for mode configuration. The converter is pin-compatible with the 14-bit LTC2261-14 and the 12/14-bit LTC2260 and LTC2259 family members, allowing a single PCB to address multiple resolution and speed targets. Technically, the device combines an internal high-bandwidth track-and-hold front end with on-chip reference and a digital error-correction pipeline. The pin-compatible family lets designers trade resolution for power: LTC2261-12 runs at 125 Msps, LTC2260-12 at 105 Msps, and LTC2259-12 at 80 Msps, while a 14-bit counterpart doubles the vertical resolution at similar throughput. Output flexibility (CMOS, DDR CMOS, DDR LVDS) lets the same part mate directly with either ASICs/FPGAs using LVDS or with low-pin-count microcontrollers using CMOS. Typical applications include cellular base-station receivers, software-defined radio, ultrasound imaging front ends, radar signal processing, and high-speed instrumentation. With 70.8 dB SNR and 85 dB SFDR, the device cleanly resolves multi-carrier IF signals and pulsed waveforms without raising the noise floor of the receive path. When designing with this device, place the analog input coupling network as close to the AIN pins as possible, provide a solid ground plane tied to the exposed pad for thermal dissipation, and decouple AVDD/OVDD with 10 uF plus 0.1 uF ceramic capacitors within 5 mm of the supply pins. Always drive the encode clock from a low-jitter source to preserve SNR at the rated input frequency. This page synthesizes distributor pricing, pin-compatible family alternatives, and practical design notes beyond what the manufacturer datasheet alone provides, including real-time stock and lead-time data sourced from major distributors.
LTC2261CUJ-14 - 14-bit 125Msps 1.8V ADC | Analog Devices
The Analog Devices LTC2261CUJ-14 is a 14-bit, 125 Msps pipelined analog-to-digital converter (ADC) optimized for ultra-low power operation from a single 1.8V analog supply, housed in a 40-lead 6mm x 6mm QFN package. It delivers 73.4 dB SNR and 85 dB SFDR over the Nyquist bandwidth, with a typical INL of ±1 LSB and DNL of ±0.3 LSB for dc-precision digitisation of high-frequency, wide-dynamic-range signals. Per the Analog Devices datasheet 226114fc, the device consumes about 125 mW at 125 Msps and supports full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS digital outputs with a separate output supply from 1.2V to 1.8V. A pipelined ADC is a high-speed successive-staged converter architecture that resolves an analog input over multiple low-resolution pipeline stages, each stage forwarding residual residue and digital data to the next clock edge. This delivers multi-Msps sample rates while trading input latency (typically a few clock cycles) for very low power per conversion. The LTC2261CUJ-14 sits at the high end of Analog Devices' ultralow-power 1.8V 14-bit family, alongside the 105 Msps LTC2260-14 and 80 Msps LTC2259-14, all of which share the same pinout and 40-pin QFN-6x6 footprint. Key features include an optional clock duty-cycle stabilizer that corrects for non-50% clock duty, shutdown and nap modes for power gating between conversions, a serial SPI port for configuration of modes and output driver behaviour, and pin-compatible 12-bit versions (LTC2261-12 / LTC2260-12 / LTC2259-12) that drop directly onto the same PCB. An integrated high-bandwidth track-and-hold and on-chip references minimise external component count. Transition noise is rated at 1.2 LSB RMS with no missing codes across the operating temperature range. Typical applications include multicarrier broadband communications receivers, cellular base-station digitiser cards, software-defined radio (SDR) front-ends, cable head-end equipment, and high-speed test instrumentation. The 1.2V to 1.8V CMOS output swing simplifies direct connection to FPGA LVCMOS banks without level shifters, while the LVDS mode enables long-distance backplane routing at full 125 Msps. Pin compatibility with the slower LTC2260-14 and LTC2259-14 lets one PCB support three speed/price tiers by changing only the ADC part number.
LTC2261IUJ-12 - 12-Bit 125Msps 1.8V Ultra-Low Power ADC | ADI
The Analog Devices LTC2261IUJ-12 is a 12-bit, 125 Msps, ultra-low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6 mm × 6 mm) package with an exposed pad. It operates from a single 1.8 V supply, drawing 124 mW at full speed while delivering ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and a low 0.3 LSB RMS transition noise with no missing codes over the industrial -40 °C to +85 °C temperature range. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes input samples through multiple cascaded low-resolution stages, each stage resolving a portion of the conversion before handing the residue to the next stage. Pipelined ADCs sit in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. They dominate applications from 10 Msps to several hundred Msps where both speed and resolution matter, especially in communications, imaging, and instrumentation front-ends. The LTC2261IUJ-12 features selectable input ranges from 1 Vp-p to 2 Vp-p, an 800 MHz full-power analog input bandwidth sample-and-hold, and an optional clock duty-cycle stabilizer for clean sampling with non-50% clock sources. The digital outputs can be configured as full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, with a separate output supply pin allowing the CMOS swing to be programmed from 1.2 V to 1.8 V for direct interface to ASICs and FPGAs. A serial SPI port provides configuration of output mode, input range, and power-down options. Typical applications include basestation receive signal paths, portable instrumentation, handheld test equipment, low-power medical imaging, software-defined radio, and general-purpose multi-channel data acquisition where thermal budget and PCB area are tight. Pin-compatible 14-bit (LTC2261-14) and lower-speed 12-bit family members (LTC2260-12 at 105 Msps, LTC2259-12 at 80 Msps) allow designers to scale resolution and sampling rate without changing the PCB footprint. Design consideration: choose CMOS outputs for low-cost FPGA connections with 1.2 V–1.8 V swing, or switch to LVDS for noise-immune long-trace routing above 100 Msps. Decouple AVDD and DVDD independently with 0.1 µF + 10 µF ceramics placed within 3 mm of the supply pins. This page combines distributor pricing, drop-in pin-compatible alternatives, and practical layout notes not duplicated in the manufacturer datasheet.
LTC2261IUJ-14 - 14-Bit 125Msps Ultra-Low Power 1.8V ADC | ADI
The Analog Devices LTC2261IUJ-14 is a 14-bit, 125 Msps ultra-low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) exposed-pad package. It is part of the LTC2261-14 / LTC2260-14 / LTC2259-14 family, which collectively offer 125/105/80 Msps sampling rates with shared pinout and digital interface options. A pipelined ADC is a high-speed successive-approximation architecture that breaks the conversion into multiple low-resolution stages operating in parallel on different clock edges, enabling sample rates of tens to hundreds of Msps while keeping per-stage power dissipation low. The LTC2261IUJ-14 targets AC performance, featuring 73.4 dB SNR and 85 dB spurious-free dynamic range (SFDR), which makes it well-suited to communications and signal-intelligence front-ends where wide dynamic range signals must be digitized cleanly. Key specifications include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over the full operating temperature range, and 1.2 LSB RMS transition noise. The digital output port is highly flexible, supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS modes, and a separate output power supply pin (OVDD) allows the CMOS swing to be programmed from 1.2 V to 1.8 V for direct interface to 1.2 V, 1.5 V, or 1.8 V logic. The 'UJ-14' ordering code combines the industrial temperature grade (-40 °C to +85 °C) with the 40-lead QFN (6x6) package and a 14-bit resolution. The part is part of Linear Technology's classic low-power 1.8 V ADC portfolio that was later absorbed into the Analog Devices data-converter catalog after the 2017 ADI/LTC merger, with datasheet document 226114fc. Typical applications include communications receivers, cellular base-station IF sampling, cable-headend digitizers, medical imaging front-ends, portable instrumentation, and non-destructive test equipment. Its ultra-low 1.8 V analog supply operation (~100 mW typical at 125 Msps) also makes it attractive for low-power field-deployed systems. When designing with the LTC2261IUJ-14, drive the analog inputs with a low-noise, wideband differential amplifier such as the AD8138 or LT1994 to realize the datasheet SNR/SFDR. Use a low-jitter differential clock source and provide well-decoupled AVDD and OVDD rails; the exposed pad must be soldered to a continuous ground plane for thermal and electrical performance. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical layout notes that go beyond the manufacturer datasheet, giving engineers a single reference for sourcing and designing with the LTC2261IUJ-14.
LTC2262CUJ-12 - 12-bit 150Msps 1.8V Low-Power ADC | Analog Devices
The Analog Devices LTC2262CUJ-12 is a 12-bit, 150 Msps pipelined analog-to-digital converter (ADC) with one differential input channel, designed for digitizing high-frequency, wide dynamic-range signals. It operates from a single 1.8 V analog supply and dissipates only 250 mW at 150 Msps, housed in a 40-lead QFN (6x6 mm) package with exposed pad for thermal dissipation. An analog-to-digital converter (ADC) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes for processing by digital systems. Pipeline ADCs use a cascaded architecture of low-resolution stages to achieve high sampling rates (>100 Msps) with good linearity, and they sit in the data-converter hierarchy between successive-approximation register (SAR) ADCs (lower speed, higher precision) and flash ADCs (highest speed, lowest resolution). The LTC2262-12 family belongs to the wider category of integrated circuits (ICs) within data acquisition systems. Key features include 70.5 dB SNR and 88 dB spurious-free dynamic range (SFDR) at 70 MHz input, an aperture delay of 200 ps, and a fully differential input that accepts single-ended or differential drive. Internal voltage reference and clock duty-cycle stabilizer simplify board design, and a separate output supply (1.5 V to 1.8 V for LVDS or 1.8 V to 3.3 V for CMOS) allows direct interfacing to FPGAs or DSPs. The LTC2262-12 uses a switched-capacitor pipelined front end and on-chip sample-and-hold, achieving excellent AC linearity even at full-scale input frequencies above 100 MHz. Pin-selectable CMOS or LVDS DDR outputs give the designer flexibility between low-EMI logic and high-speed serial interface, while an optional LVDS PECL clock input supports external jitter cleaning. Typical applications include communications infrastructure (multi-carrier GSM, W-CDMA, LTE base-station receivers), radar and lidar signal chains, medical imaging front ends, and high-speed test instrumentation. The wide input bandwidth and high SFDR make it equally suited to software-defined radio (SDR) and spectrum analysis front ends where intermodulation distortion must be minimized. When designing with this part, treat the exposed pad as the primary thermal path and solder it to a continuous ground plane with multiple vias. Drive the analog inputs through a balun or transformer for optimum second-harmonic performance, and keep digital outputs (especially LVDS) routed with 100 ohm differential impedance and length-matched traces. Use the internal reference for ease of design or an external reference for gain-accuracy-critical applications. This page synthesizes distributor pricing, AEC-Q100 compliance status, drop-in ADC alternatives in the same 40-QFN footprint, and practical PCB layout guidance not all collected in the Analog Devices datasheet.
LTC2262IUJ-12 - 12-Bit 150Msps Ultralow Power 1.8V ADC | ADI
The Analog Devices LTC2262IUJ-12 is a 12-bit, 150 Msps sampling analog-to-digital converter (ADC) designed for digitizing high-frequency, wide-dynamic-range signals in demanding communications and instrumentation applications. Housed in a 40-lead QFN (6 mm x 6 mm) package with exposed pad, the device pairs 70.5 dB SNR with 88 dB spurious-free dynamic range (SFDR) and a 150 Msps conversion rate, while consuming only a fraction of the power typically required by pipelined ADCs in this speed class. An ADC (analog-to-digital converter) is a data-conversion integrated circuit that samples continuous analog input voltages and outputs discrete digital codes, forming the bridge between the analog front-end and the digital signal-processing chain of a system. ADC ICs belong to the data-converter product family, which sits within the broader mixed-signal semiconductor hierarchy alongside digital-to-analog converters (DACs) and clock-and-timing ICs. Key features of the LTC2262-12 include ultralow 0.17 ps RMS aperture jitter, which enables accurate undersampling of IF frequencies in communications receivers without degrading noise performance; a differential input architecture for common-mode noise rejection; an integrated high-bandwidth track-and-hold; and CMOS-compatible parallel digital outputs. The exposed-pad QFN-40 package provides a low thermal-resistance path for reliable operation at full speed over the -40 C to +85 C industrial temperature range. Typical applications include cellular base-station receiver IF digitizers, software-defined radio (SDR) front-ends, medical imaging ultrasound signal chains, cable-headend modems, and high-speed multi-channel data-acquisition cards. The wide full-power bandwidth and excellent SFDR at high input frequencies also make the part well-suited to radar and spectrum-analysis equipment. When designing with the LTC2262-12, follow Analog Devices' reference-layout guidance for the QFN-40 exposed pad: use a solid ground plane stitched with vias beneath the pad, place the front-end anti-alias filter and the ADC input network as close to the analog inputs as possible, and decouple the 1.8 V analog and 1.8 V digital rails with low-ESR ceramic capacitors to preserve the datasheet's SNR and SFDR numbers. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical layout guidance that goes beyond the manufacturer datasheet to help engineers evaluate and qualify the LTC2262IUJ-12 quickly.
LTC2263CUJ-12 - 12-Bit 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2263CUJ-12 is a 12-bit, 25 Msps, low-power dual pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6 mm x 6 mm) package with exposed thermal pad. It integrates two simultaneously-sampling ADC channels, each with a sample-and-hold front end, providing true 12-bit linearity (typical ±0.3 LSB INL, ±0.1 LSB DNL) with no missing codes over temperature, and only 0.3 LSB RMS transition noise. The part operates on a single 1.8 V supply, drawing approximately 30 mW per channel at full speed, and offers shutdown and nap modes for portable applications. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed Nyquist ADC architecture that resolves the input sample in a sequence of low-resolution stage conversions. Each stage produces a partial digital result and a residue that is amplified and passed to the next stage. This pipelining allows one conversion to be in progress while the next sample is being acquired, giving sample rates from a few Msps up to several hundred Msps. Pipelined ADCs sit in the signal-chain hierarchy: sensor -> analog front end -> ADC -> digital processing. They are the workhorse architecture for communications, imaging, and instrumentation. Key features of the LTC2263CUJ-12 include 800 MHz full-power input bandwidth, flexible serial LVDS digital outputs (1-lane or 2-lane mode), an SPI port for per-channel configuration of gain, offset, and channel selection, and pin compatibility with the 14-bit LTC2263-14 and the higher-speed LTC2264-12 (40 Msps) / LTC2265-12 (65 Msps) family members. CMOS and DDR LVDS output modes are selectable. Typical applications include cellular basestation receivers, software-defined radio (SDR), portable medical imaging, low-power ultrasound, multi-channel data acquisition, and handheld test instrumentation where dual-channel simultaneous sampling reduces system cost and board area. The wide input bandwidth also allows undersampling of IF signals in communications systems. When designing with the LTC2263CUJ-12, decouple AVDD and DVDD supplies with 1 muF ceramic capacitors placed as close to the pins as possible, and provide a clean clock source with low jitter - the SNR floor of an ADC is dominated by the aperture uncertainty of the sampling clock. Use the exposed pad as the primary thermal and ground return path. This page combines verified distributor stock data, drop-in pin-compatible alternatives, and practical design notes that go beyond what the manufacturer datasheet alone provides - useful for engineers evaluating the LTC2263-12 family for new designs or second-source qualification.
LTC2263CUJ-14 - Dual 14-Bit 25Msps Low-Power ADC | Analog Devices
The Analog Devices LTC2263CUJ-14 is a 14-bit, 25Msps, low-power dual-channel pipelined analog-to-digital converter housed in a 40-pin 6x6mm QFN package. Each of the two simultaneously-sampling ADC channels features 73.7 dB SNR and 90 dB SFDR, with total power consumption of just 94 mW (47 mW per channel) from a single 1.8 V supply. A dual ADC (dual-channel analog-to-digital converter) is a component that integrates two independent sampling channels on a single die, allowing simultaneous capture of two analog signals at the same clock instant. This dual architecture is widely used in communications receivers where I/Q baseband signals must be sampled synchronously, in diversity antenna systems, and in any multi-channel instrumentation application. The LTC2263CUJ-14 belongs to the broader pipelined ADC family within the data acquisition IC category, which sits hierarchically under converter ICs and signal chain semiconductors. The device includes selectable 1V P-P to 2V P-P input ranges, an 800 MHz full-power bandwidth sample-and-hold, and serial LVDS outputs configurable for 1-bit or 2-bit per channel modes. DC accuracy is excellent, with ±1 LSB INL (typical), ±0.3 LSB DNL (typical), and no missing codes over temperature. The low 1.2 LSB RMS transition noise ensures clean digital output even at full-scale inputs. Pin-compatible 14-bit and 12-bit versions allow system designers to migrate between resolutions without PCB rework, while the integrated SPI configuration port, shutdown, and nap modes simplify power management. According to the manufacturer datasheet, the recommended PCB layout requires a clean unbroken ground plane with the first internal layer dedicated to ground beneath the ADC. Typical applications include software-defined radio (SDR), cellular base-station receivers, portable instrumentation, and low-power medical imaging. The wide 800 MHz input bandwidth makes the part particularly attractive for undersampling IF signals in communications receivers. When laying out the PCB, ensure that analog input traces are routed as differential pairs over a continuous ground plane to preserve the 73.7 dB SNR. Place the 1.8V supply decoupling network within 5 mm of the AVDD pins to suppress switching-noise coupling. This page synthesizes distributor pricing, drop-in pin-compatible alternatives from the same ADC family, and practical PCB/layout guidance that goes beyond what is found in the manufacturer datasheet alone.
LTC2263IUJ-14 - 14-Bit 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2263IUJ-14 is a 14-bit, 25 Msps, dual-channel, low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) exposed-pad package. Each of its two simultaneously-sampling channels digitizes high-frequency, wide-dynamic-range signals with ±1 LSB (typ) INL, ±0.3 LSB (typ) DNL, no missing codes over temperature, and 1.2 LSB RMS transition noise. The digital outputs are serial LVDS, configurable as 2-lane or 1-lane mode per channel to minimize data-line count. An ADC (analog-to-digital converter) is a mixed-signal semiconductor that samples continuous analog input voltages and produces discrete digital codes at a fixed sample rate; pipelined ADCs use a cascade of low-resolution stages to achieve high throughput at modest power, making them the workhorse architecture for communications, imaging, and instrumentation. The LTC2263IUJ-14 belongs to the power-management-and-conversion family and specifically to the pipelined ADC sub-class, integrating two simultaneously-sampling converters, internal reference, and LVDS drivers in one IC. Its 1.8 V single-supply operation simplifies power-tree design and pairs naturally with LVDS-capable FPGAs. Key features of the LTC2263IUJ-14 include 73.4 dB SNR, 90 dB SFDR (typical), 25 Msps per-channel sample rate, serial LVDS output with 2-lane or 1-lane option, internal bandgap reference, low power dissipation (typical 60 mW per channel at 25 Msps), and an operating temperature range of -40°C to +85°C (I-grade). The exposed pad on the QFN-40 package provides a low thermal-resistance path (θJA of approximately 33°C/W), enabling compact multi-channel designs without external heatsinking. Typical applications for the LTC2263IUJ-14 include high-speed data acquisition, communications receivers, digital oscilloscopes, medical imaging front-ends, multi-channel software-defined radio (SDR), and portable instrumentation. Its dual simultaneous-sampling architecture is especially suited to I/Q baseband, diversity receivers, and time-interleaved measurement systems where channel-to-channel phase coherence is critical. When designing with this ADC, maintain a multilayer PCB with an unbroken internal ground plane beneath the device, drive each analog input differentially for best SFDR, and decouple the 1.8 V supply with 1 µF and 0.1 µF ceramics placed within a few millimetres of the supply pins. The exposed pad must be soldered to a low-impedance ground plane to achieve the rated thermal and electrical performance.
LTC2264CUJ-14 - 14-Bit 40Msps Dual ADC, Serial LVDS, 40-QFN | ADI
The Analog Devices LTC2264CUJ-14 is a 14-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 40-lead QFN (6x6 mm) package with an exposed thermal pad. It provides two simultaneous 14-bit conversions at 40 Msps per channel with serial LVDS digital outputs, and operates from a single 1.8 V supply. The serial LVDS interface minimizes data-line count and eases board routing in multi-channel systems. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that uses multiple cascaded low-resolution stages to digitize a continuous analog signal, with each stage resolving a portion of the input code while subsequent stages refine the result. Pipelined ADCs occupy the middle ground between flash converters (fastest, lowest resolution) and successive-approximation ADCs (slowest, highest resolution), making them ideal for communications, instrumentation, and imaging applications requiring 10-16 bits at 20-250 Msps. The LTC2264-14 family belongs to the higher-level hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features of the LTC2264CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and a low 1.2 LSB RMS transition noise. The digital interface can be configured for either 1-lane (one bit per channel) or 2-lane (two bits per channel) LVDS output. The flexible serial or parallel programming interface supports shutdown and nap modes, output format selection, channel selection, and bit-orientation control. The LTC2264-14 architecture combines a low-jitter differential sample-and-hold front end with a multi-stage switched-capacitor pipeline, achieving excellent AC performance (73.1 dB SNR, 88 dB SFDR typical at 4.9 MHz input) while consuming only 69 mW per channel. The part is part of a pin-compatible family with the 65 Msps LTC2265-14 and the 25 Msps LTC2263-14, enabling a single PCB design to support multiple speed grades. Typical applications include communications receivers, cell base stations, digital predistortion feedback paths, handheld signal analyzers, medical imaging front ends, and non-destructive ultrasonic testing. The low power dissipation (138 mW total) and small QFN package make it well suited to portable and densely populated multi-channel systems. When designing with the LTC2264CUJ-14, drive each analog input with a low-jitter differential amplifier to preserve SNR, and route the serial LVDS pairs with controlled 100 Ω differential impedance. The exposed pad must be soldered to a low-impedance ground plane for thermal and electrical performance. Decouple all four supply pins with 0.1 µF and 10 µF capacitors placed as close to the IC as possible. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2264IUJ-12 - 12-Bit 40Msps Dual ADC, 40-QFN | ADI
The Analog Devices LTC2264IUJ-12 is a 12-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 40-lead QFN (6 mm × 6 mm) package with an exposed pad. It integrates two ADC channels that sample in lock-step, supports analog inputs up to 2 Vp-p, and serial LVDS digital outputs in either 1-lane or 2-lane mode to minimize data-line count. According to the ADI datasheet, the converter achieves ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and 0.3 LSB RMS transition noise with no missing codes over temperature. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time continuous-amplitude analog signals into discrete-time discrete-amplitude digital words. The pipelined ADC architecture employed in the LTC2264-12 family uses multiple low-resolution stages to digitize a sample at high speed with low latency, making it the workhorse of communications, instrumentation, and imaging front-ends. Within the broader taxonomy, this part is a successive-stage pipelined ADC > SAR/pipelined hybrid > data converter > mixed-signal IC > semiconductor. Key features include 73.4 dB SNR and 90 dB SFDR at the Nyquist input frequency, a wide 140 MHz full-power bandwidth, low power dissipation, and an external reference for full-scale range programming. The 40-QFN package with exposed thermal pad provides a low θJA path for high-density multi-channel layouts. Per the ADI datasheet, the part supports both CMOS and LVDS output modes and is offered in commercial (LTC2264C) and industrial (LTC2264I) temperature grades; the LTC2264IUJ-12 is the industrial-temperature 40-QFN variant. The part fits applications such as baseband I/Q digitization in software-defined radio, multi-channel data acquisition in industrial imaging, ultrasound beamformer front-ends, and portable or battery-powered instrumentation where simultaneous-sampling dual channels at moderate sample rates are required. Its serial LVDS interface simplifies board routing and reduces digital switching noise coupling into the analog inputs. A critical design consideration is that LVDS outputs require a 100 Ω differential termination at the receiver and that the analog input common-mode voltage be set within the part's specified range; mis-terminated LVDS lines will degrade SNR and SFDR. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2264IUJ-14 - 14-Bit 40Msps Dual ADC | Analog Devices | Industrial
The Analog Devices LTC2264IUJ-14 is a 14-bit, 40 Msps low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6mm x 6mm) package. The LTC2264 family is offered in three speed grades — 25 Msps, 40 Msps, and 65 Msps — with the "-14" suffix denoting the 14-bit resolution and the "40 Msps" speed grade is identified by the part's IUJ-14 marking. The dual-channel architecture integrates two complete ADC channels on a single die, enabling simultaneous sampling for time-interleaved or I/Q signal chain applications. A pipelined ADC (also called a pipeline converter) is a multi-stage successive-approximation architecture that resolves one or two bits per clock cycle across cascaded gain stages. The pipelined topology achieves high sample rates at moderate-to-high resolution with low latency relative to delta-sigma converters and far better dynamic range than flash ADCs at this resolution. Pipelined ADCs sit in the broader data-converter hierarchy: ADC -> Nyquist-rate ADC -> pipelined ADC -> mixed-signal IC -> semiconductor. Within Analog Devices' portfolio, the LTC226x family occupies the low-power, dual-channel pipelined segment. Key specifications of the LTC2264IUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), and guaranteed no missing codes over the full industrial temperature range. Transition noise is specified at 1.2 LSB RMS, contributing to a clean spurious-free dynamic range. The digital outputs use a serial LVDS interface, which minimizes the number of board traces required between the ADC and the downstream FPGA or ASIC. Each channel can be configured to output two bits per clock (2-lane mode) for higher throughput or one bit per clock (1-lane mode) for lower pin-count routing. The part operates from a single 1.8V analog supply and is configured through a serial SPI port. Auxiliary features include shutdown and nap power-down modes, an 800 MHz full-power sample-and-hold bandwidth, and pin compatibility across the 14-bit and 12-bit family members (LTC2264-14/LTC2264-12/LTC2265-14). The pin-compatible 12-bit and 14-bit options allow board-level reuse when the application can trade resolution for SNR. Typical applications include diversity radio receivers, I/Q baseband digitizers, medical imaging front-ends, multi-channel data acquisition systems, and communications test equipment. The dual-channel matched-pair architecture is well-suited to phased-array antenna systems and any signal chain that requires coherent dual-channel sampling. When designing with the LTC2264IUJ-14, pay careful attention to the analog input network: the ADC's S/H front-end benefits from a wideband transformer or differential driver, and LVDS traces must be length-matched and routed with controlled 100-ohm differential impedance. Using the SPI port to enable the nap mode between acquisition bursts can reduce power consumption significantly in duty-cycled applications. This page consolidates distributor pricing, pin-compatible alternatives from the same LTC226x family, and practical design notes that complement (rather than duplicate) the official Analog Devices datasheet.
LTC2265CUJ-12 - 12-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2265CUJ-12 is a 12-bit, 65Msps low-power dual analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package with exposed pad. It integrates two simultaneously-sampling 12-bit pipelined ADC cores, accepts 2 differential or single-ended analog inputs, and is specified for 65 Msps per channel, making it suitable for digitizing high-frequency wide-dynamic-range signals in communications and instrumentation. An analog-to-digital converter (ADC) is a semiconductor device that converts continuous analog signals into discrete digital codes. The pipelined ADC architecture, used by the LTC2265CUJ-12, employs multiple cascaded low-resolution stages with sample-and-hold amplifiers and digital error correction. This architecture sits within the broader hierarchy of: ADC -> data converter -> mixed-signal IC -> power management and signal chain semiconductor. Pipelined ADCs are favored over successive-approximation (SAR) types at sample rates above ~10 Msps because they balance speed, resolution and power consumption. Key features of the LTC2265CUJ-12 include dual 12-bit simultaneous-sampling channels at 65 Msps each, low power consumption, an LVDS or CMOS selectable digital interface, integrated input buffers and a flexible clock input. The 40-lead QFN (6x6) package provides a small footprint while the exposed thermal pad ensures low thermal resistance (theta-JA approximately 30 C/W) suitable for fanless embedded designs. Per the manufacturer datasheet, the part supports an analog supply near 1.8V and a digital supply near 1.8V, both essential for low-power operation. The LTC2265CUJ-12 uses a multi-stage pipeline per channel with proprietary SHA front-end and on-chip dither, achieving effective spurious-free dynamic range (SFDR) well above Nyquist with no missing codes. The dual simultaneous sampling enables I/Q demodulation or orthogonal channel capture without external synchronization, a distinct advantage over multiplexed ADCs. Typical applications include cellular base-station receivers, IF sampling in software-defined radio, medical imaging front-ends such as ultrasound, multi-channel data acquisition and industrial process control. Designers commonly pair the ADC with an Analog Devices low-noise LDO such as the LT3042 and a high-speed differential amplifier such as the ADA4927 to realize a complete signal chain. When designing with this device, maintain a continuous clock at the ENC input, decouple AVDD and DVDD with 1uF and 0.1uF ceramic capacitors placed within 2mm of the supply pins, and provide a clean low-jitter clock. Input common-mode and input amplitude must conform to the datasheet's recommended settings to preserve SFDR. This page synthesizes distributor pricing, drop-in same-package alternatives and practical design notes not found in the manufacturer datasheet alone, helping engineers shorten selection and qualification cycles.