EPM5192AGC vs EPM5192AGC-20 مقایسه
مقایسه دقیق کنار به کنار EPM5192AGC توسط Altera و EPM5192AGC-20 توسط Intel. مشخصات کلیدی، پارامترهای الکتریکی، بسته‌بندی، وضعیت چرخه عمر، قیمت‌گذاری و موجودی را مقایسه کنید تا بهترین قطعه را برای نیازهای طراحی خود تعیین کنید.
مقایسه مشخصات
| پارامتر | EPM5192AGC | EPM5192AGC-20 |
|---|---|---|
| برند | Altera | Intel |
| دسته‌بندی | FPGA & CPLD | FPGA & CPLD |
| وضعیت چرخه عمر | Obsolete | Obsolete |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | EPLD (EEPLD, UV-erasable) |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | — |
| بسته‌بندی | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | PGA-132 (ceramic windowed, 'GC') |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| دمای کاری | [DATA_NEEDED: operating temperature range] | 0C to 70C (commercial) |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | Yes (pattern read-back protected) |
| ولتاژ تغذیه | [DATA_NEEDED: VCC nominal and tolerance] | — |
| نوع نصب | Through-hole (Pin Grid Array) | Through-hole (PGA socket) |
| وضعیت RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Usable Gates | — | 12,000 |
| Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz (max) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Logic Array Blocks (LABs) | — | 8 |
| Dedicated I/O Pins | — | 96 |
| Programming Interface | — | IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5 V ISP) |