5CSEBA5U19I7N vs 5CSEBA5U19C8N Comparaison
Comparaison détaillée côte à côte de 5CSEBA5U19I7N par Intel et 5CSEBA5U19C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA5U19I7N | 5CSEBA5U19C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $119,85 | $195,00 |
| Product Type | SoC FPGA (System-on-Chip FPGA) | — |
| Series | Cyclone V SE | — |
| Logic Elements | 85,000 | 85,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Core Frequency | 800 MHz (typical), up to 925 MHz | — |
| Process Technology | 28 nm TSMC low-power | 28 nm TSMC |
| Boîtier | 484-pin UBG (UFBGA) 19x19 mm | 484-UBGA (U19, 19x19 mm) |
| Tension d'alimentation | 1.1 V core | — |
| FPGA User I/O | 66 (per datasheet front-page snippet) | — |
| Embedded Memory | Approximately 4,450 Kbits | 3.88 Mbit |
| DSP Blocks | 87 variable-precision (18x18 multipliers) | — |
| Transceivers | Up to 5 Gbps (Cyclone V SE feature) | — |
| HPS Peripherals | USB 2.0 OTG, EMAC, CAN, SPI, I2C, UART, SD/MMC, NAND | — |
| Température de fonctionnement | -40C to +100C (Industrial grade, suffix I) | 0C to +85C (commercial) |
| Type de montage | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | Compliant (per Heisener listing and product family) | Compliant |
| Family | — | Cyclone V SE (SoC FPGA) |
| Adaptive Logic Modules (ALMs) | — | 32,070 ALM |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Core Maximum Frequency | — | 925 MHz (datasheet); 600 MHz commercial speed grade |
| L1 Cache (Instruction) | — | 2 x 32 kB |
| L1 Cache (Data) | — | 2 x 32 kB |
| L2 Cache | — | 512 kB shared |
| FPGA User I/Os | — | 66 I/O |
| Core Voltage | — | 1.1 V |
| Ball Pitch | — | [DATA_NEEDED: ball pitch in mm] |
| Speed Grade | — | C8 (0.85 ns, commercial) |