ADC12DL040CIVS vs ADC12040CIVY Comparaison
Comparaison détaillée côte à côte de ADC12DL040CIVS par Texas Instruments et ADC12040CIVY par Texas Instruments. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Texas Instruments
ADC12DL040CIVS - Dual 12-Bit 40 MSPS 3V ADC | Texas Instruments
ADC12DL040CIVS NrndTexas Instruments
ADC12040CIVY - 12-Bit 40MSPS Pipelined ADC | Texas Instruments
ADC12040CIVY ✓ ActifComparaison des spécifications
| Paramètre | ADC12DL040CIVS | ADC12040CIVY |
|---|---|---|
| Marque | Texas Instruments | Texas Instruments |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | NRND | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $11,85 | $5,52 |
| Résolution | 12 Bits | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 1 input |
| Sample Rate (per channel) | 40 MSPS | — |
| Architecture | Pipelined CMOS | Pipelined |
| Analog Supply Voltage | 3.0 V (2.7 V to 3.6 V range) | — |
| Digital Output Driver Supply | 2.4 V to 3.6 V (separate DVDD) | — |
| Power Dissipation (typical) | 210 mW | — |
| Power-Down Mode | Yes | — |
| SNR (fIN = 10 MHz) | 69 dB (typical) | — |
| SFDR (fIN = 10 MHz) | 85 dB (typical) | — |
| DNL (Differential Non-Linearity) | ±0.3 LSB (typical) | — |
| INL (Integral Non-Linearity) | [DATA_NEEDED: INL spec] | — |
| Internal Reference | Yes (factory-trimmed, not user-adjustable) | — |
| Sample-and-Hold | Internal, dual | — |
| Duty Cycle Stabilizer | Yes | — |
| Multiplexed Output Mode | Yes (channels share single 12-bit bus) | — |
| Output Format | Straight Binary, offset binary, 2's complement (per pin strapping) | — |
| Input Clock | Single-ended or differential; 50 Ω terminated internally | — |
| Température de fonctionnement | -40 °C to +85 °C (industrial) | — |
| Boîtier | 64-pin TQFP (PAG) 10x10 mm, surface-mount | 32-LQFP (NEY) 7x7 mm |
| MSL (Moisture Sensitivity Level) | [DATA_NEEDED: MSL level] | — |
| Lead Finish / RoHS | Lead-free / RoHS status depends on orderable suffix (see datasheet ordering info) | — |
| Fréquence d'échantillonnage | — | 40 MSPS (min 40 MSPS over temperature) |
| Tension d'alimentation | — | +5V ±5% (single supply) |
| Power Consumption | — | 340 mW (typ) at 40 MHz |
| Differential Non-Linearity (DNL) | — | ±0.4 LSB (typ) |
| Signal-to-Noise Ratio (SNR) | — | 69 dB (typ) at fIN = 10 MHz |
| Effective Number of Bits (ENOB) | — | 11.2 bits (typ) at fIN = 10 MHz |
| Input Type | — | Differential (single-ended capable) |
| Reference Type | — | External, with internal buffer |
| Digital Output Interface | — | Parallel, CMOS, straight binary |
| Digital Output Logic Levels | — | 2.35V to 5V compatible |
| Power Down Mode | — | On-chip (low quiescent between conversions) |
| Plage de température de fonctionnement | — | -40C to +85C (industrial) |
| Type de montage | — | Surface Mount |
| Pin Family Compatibility | — | Pin compatible with ADC12010, ADC12020, ADC12L063, ADC12L066 |
| Statut RoHS | — | Compliant (NOPB suffix variants only; check exact suffix) |