EP1810JC-25 vs EP1810JC-35 Comparaison
Comparaison détaillée côte à côte de EP1810JC-25 par Intel et EP1810JC-35 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810JC-25 | EP1810JC-35 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $6,80 | $5,48 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Température de fonctionnement | -40 °C to 85 °C (industrial, per distributor listings) | — |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| Boîtier | 28-pin ceramic DIP (J) with quartz window | — |
| Type de montage | Through-hole | Surface Mount (J-Lead) |
| Erasure Method | UV light (windowed package) | UV (quartz-windowed ceramic package) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per Altera listing) |
| Statut du cycle de vie | NRND (Not Recommended for New Designs) | — |
| Device Family | — | Classic EPLD (EP1810) |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Propagation Delay (tpd) | — | 35 ns (max) |
| Fréquence d'horloge maximale | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Plage de température de fonctionnement | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |