EP1810JC-35 - 48-Macrocell UV EPLD, 35ns, CQCC-68 | Intel / Altera
Référence : EP1810JC-35 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $6 | $6,00 |
| 10 | $5.83 | $58,30 |
| 100 | $5.65 | $565,00 |
| 200 | $5.65 | $1 130,00 |
| 500 | $5.48 | $2 740,00 |
EP1810JC-35 Présentation
What is a UV EPLD? An EPLD (Erasable Programmable Logic Device) is a class of programmable logic that combines AND/OR array structures with programmable macrocells and a programmable interconnect network. The UV-erasable variant (UVPLD) is programmed electrically and erased by exposing the die to ultraviolet light through a quartz window, allowing multiple design cycles during prototyping and field service. UV EPLDs sit between simple PAL/GAL devices and modern flash-based CPLDs in the programmable logic hierarchy, and they have been widely used in telecom, industrial, and defense systems since the mid-1980s because they provide deterministic propagation delay, non-volatile configuration, and superior pin-locking for through-hole PCB designs.
Key features of the EP1810JC-35 include 48 macrocells, 35 ns worst-case pin-to-pin propagation delay (tpd), a maximum toggle frequency in the tens of megahertz range, and 68 J-lead ceramic interconnect pins rated for commercial-grade 0°C to 70°C operation. The device is fabricated in CMOS technology for low power consumption, supports 5 V standard logic interfaces, and provides a programmable output macrocell with configurable register/bypass, feedback, and tri-state options that simplify bus-interface, address-decoding, and state-machine integration.
The EP1810JC-35 implements a classic sum-of-products logic architecture with each macrocell fed by a programmable AND array and feeding a programmable OR/registered output stage. This deterministic architecture, combined with non-volatile UV-erasable configuration memory, makes the part attractive for designs that require predictable timing analysis without needing the configuration controller or boot PROM required by SRAM-based FPGAs. The device is one of the slowest members of the EP1810 family and is typically selected where 35 ns timing comfortably meets the system clock period rather than requiring the 25 ns or 20 ns -25/-20 speed grades.
Typical applications include glue-logic replacement for 74LS/74AS TTL in legacy telecom backplanes, address decoding and wait-state generation in 8086/80286 microprocessor systems, bus arbitration and interrupt controllers in industrial control cards, and avionics ground-test fixtures where non-volatile, deterministic logic is required and field-reprogrammability via UV erasure is acceptable. The 68-pin ceramic J-leaded package also supports MIL-STD-883B screening variants of the same die (EP1810GM/883B family) for harsher environments.
When designing with the EP1810JC-35, verify timing against the 35 ns propagation delay budget, ensure programming is performed with a verified EP1810 device programmer (modern third-party programmers still support this legacy family), and consider migrating to a pin-compatible flash-based MAX 7000-series CPLD (such as EPM7128S in the same PLCC-84 / CQCC-68 footprint) for new designs where in-system reprogrammability is desired. Always use a quartz-windowed ceramic package if UV erasure is needed; otherwise, specify the OTP one-time-programmable variant for production boards.
This page synthesizes distributor inventory, parametric data, and practical migration guidance not always found in the original Altera datasheet, helping engineers evaluate legacy EPLD options for both sustaining-engineering and modernization projects.
Alternatives de remplacement direct pour EP1810JC-35 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP1810JC-35 (même facteur de forme et même empreinte) — différant par Mounting Type, Operating Temperature, Technology, Package, Package Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP1810JC-25
✅ Remplacement direct✓ En stock
$6.8 / unité
Voir la fiche technique →EP1810GM883B
✅ Remplacement direct✓ En stock
$125.4 / unité
Voir la fiche technique →EP1810GM883
✅ Remplacement direct✓ En stock
$175 / unité
Voir la fiche technique →EP1810GM/883B
✅ Remplacement direct✓ En stock
$49.75 / unité
Voir la fiche technique →EP1810GC-35
✅ Remplacement direct✓ En stock
$177.12 / unité
Voir la fiche technique →EP1810GC-35AB
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP1810GI-45
✅ Remplacement direct✓ En stock
$56.4 / unité
Voir la fiche technique →EP1810JC-35 Valeurs maximales et caractéristiques électriques
| Device Family | Classic EPLD (EP1810) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | 48 |
| Propagation Delay (tpd) | 35 ns (max) |
| Process Technology | CMOS |
| Supply Voltage (Vcc) | 5 V (nominal) |
| Maximum Supply Voltage | 5.25 V (per distributor listing) |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | 68 |
| Terminal Form | J-Bend |
| Plage de température de fonctionnement | 0°C to 70°C (Commercial) |
| Temperature Grade | Commercial |
| Erasure Method | UV (quartz-windowed ceramic package) |
| Statut RoHS | Compliant (per Altera listing) |
| Lead-Free Status | Lead-free (per distributor listing) |
| Type de montage | Surface Mount (J-Lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs |
Guide de configuration des broches du EP1810JC-35 cqcc-68 (ceramic j-lead chip carrier, qccj)
Configuration des broches du EP1810JC-35 (boîtier cqcc-68 (ceramic j-lead chip carrier, qccj)). Ce circuit intégré numérique comprend des GPIO, des interfaces de communication (UART, SPI, I2C) et des broches d'alimentation. Consultez la fiche technique du fabricant pour les fonctions alternatives des broches et les options de configuration. Indispensable pour la conception de systèmes embarqués et la conception de circuits imprimés.
Aucune donnée de brochage détaillée disponible pour EP1810JC-35.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
EP1810JC-35 convient pour 6 applications: Legacy Telecom Backplane Glue Logic, Industrial Control Card State Machine, 8086/80286 Microprocessor Address Decoder, Bus Arbitration and Interrupt Controller, Avionics Ground-Test Fixture Logic, Legacy Peripheral Adapter Card.
Legacy Telecom Backplane Glue Logic
The EP1810JC-35 is well-suited to legacy telecom backplane glue-logic replacement where 48 macrocells, 35 ns propagation delay, and 5 V CMOS interfaces integrate address decoding, bus arbitration, and interrupt control previously implemented in 74LS/74AS TTL. The 35 ns tpd comfortably meets typical backplane clock periods in the tens of MHz, and the UV-erasable non-volatile configuration enables field re-programmability for protocol updates. The CQCC-68 J-lead ceramic package supports through-hole or socketed assembly typical of telecom line-card designs, and the part's 5 V interface is directly compatible with legacy TTL signaling without level shifters.
Recommandé
Industrial Control Card State Machine
The EP1810JC-35 fits industrial control card state-machine integration where deterministic timing and non-volatile configuration are required. Its 48 macrocells accommodate multi-state controllers for motor sequencing, conveyor logic, and sensor-fusion arbitration, while the 35 ns tpd provides predictable timing analysis for safety-critical control loops. The CMOS process technology keeps standby power low for always-on industrial controllers, and the 5 V supply matches the prevailing PLC and sensor-interface voltage rails. UV erasability allows field updates during commissioning, and the commercial 0-70°C range covers most factory-floor environments when paired with sealed enclosures.
Recommandé
8086/80286 Microprocessor Address Decoder
The EP1810JC-35 is ideal for 8086/80286-era microprocessor address decoding and wait-state generation. Its 48 macrocells implement complex address maps, chip-select logic, and READY/WAIT-state generators in a single device, replacing multiple 74LS138 / 74LS139 decoders and discrete gates. The 35 ns propagation delay fits the access-time budget of these legacy CPUs at typical 8-10 MHz bus clocks, and the 5 V CMOS interface directly connects to the 8086 address and control bus without buffering. UV-erasable non-volatile configuration simplifies production programming and field servicing.
Recommandé
Bus Arbitration and Interrupt Controller
The EP1810JC-35 integrates multi-master bus arbitration and interrupt priority controllers in legacy VMEbus and Multibus systems. Its 48 macrocells encode priority encoders, daisy-chain arbiters, and vector-interrupt logic that previously required 74LS/AS TTL MSI packages, while the 35 ns propagation delay handles arbitration propagation within one bus cycle at moderate clock rates. The device's registered macrocell outputs simplify edge-triggered arbitration protocol implementation, and its 5 V CMOS signaling matches legacy backplane electrical specifications. CQCC-68 packaging supports socketed field-replacement strategies.
Recommandé
Avionics Ground-Test Fixture Logic
The EP1810JC-35 supports avionics ground-test fixture and bench-test equipment logic where deterministic timing and field re-programmability are essential. Its 35 ns propagation delay fits MIL-1553 and ARINC 429 test fixtures that operate at moderate data rates, and its 48-macrocell capacity implements pattern generators, protocol monitors, and stimulus-response comparators in one device. The UV-erasable non-volatile configuration enables fixture updates as new aircraft protocols are validated, while the CQCC-68 ceramic package tolerates bench-environment thermal cycling and ESD events better than plastic alternatives.
Recommandé
Legacy Peripheral Adapter Card
The EP1810JC-35 is widely deployed in legacy peripheral adapter cards such as SCSI controllers, parallel I/O expanders, and GPIB interface boards. Its 48 macrocells implement command decoders, DMA handshake logic, and protocol-state machines, while the 35 ns tpd matches the timing requirements of these moderate-speed parallel buses. The 5 V CMOS interface is directly compatible with peripheral driver/receiver chips of the era, and the UV-erasable ceramic CQCC-68 package supports OEM qualification cycles with multiple design revisions before OTP production units are committed.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP1810JC-35 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP1810JC-25 | EP1810GM883B | EP1810GC-35 | EP1810GI-45 | EP1810GM/883B |
|---|---|---|---|---|---|---|
| Package | CQCC-68 (QCCJ, J-Lead) | CQCC-68 (QCCJ, J-Lead) - same | Ceramic PGA equivalent - same die, different package | CQCC-68 (Gull-Wing) - same footprint, different lead form | CQCC-68 (industrial temp) - same | Ceramic PGA equivalent - same die, different package |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Number of Macrocells | 48 | 48 (same) | 48 (same) | 48 (same) | 48 (same) | 48 (same) |
| Propagation Delay (tpd) | 35 ns | 25 ns (~29% faster) | 35 ns (same) | 35 ns (same) | 45 ns (~29% slower) | 35 ns (same) |
| Process Technology | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0°C to +70°C (Commercial) | 0°C to +70°C (Commercial) | -55°C to +125°C (Mil-Std-883B) | 0°C to +70°C (Commercial) | -40°C to +85°C (Industrial) | -55°C to +125°C (Mil-Std-883B) |
| Erasure Method | UV (ceramic window) | UV (ceramic window) | UV (ceramic window, Mil grade) | UV (ceramic window) | UV (industrial temp ceramic) | UV (ceramic window, Mil-Std-883B) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Faster speed grade available in identical CQCC-68 package (vs EP1810JC-25)
- Military temperature range available in same die (vs EP1810GM883B)
- Industrial temperature range variant with extended tolerance (vs EP1810GI-45)
Notes de conception
Estimated: confirm propagation-delay budget before substituting a slower speed grade. The EP1810GI-45 offers 45 ns tpd versus the EP1810JC-35's 35 ns, a ~29% slowdown that may violate your timing closure if your design relies on the 35 ns budget margin. Conversely, moving up to the EP1810JC-25 (25 ns tpd) gives 28% timing margin improvement at the same price band. According to Altera, all EP1810 speed grades share identical JTAG programming and functional behavior, so timing verification is the only design risk when swapping grades.
Estimated: the ceramic CQCC-68 J-lead package of the EP1810JC-35 has no exposed thermal pad and is rated for commercial 0-70°C operation. For higher ambient temperatures or higher toggle activity, switch to the EP1810GI-45 industrial-temperature grade (-40°C to +85°C) or the EP1810GM883B Mil-Std-883B variant (-55°C to +125°C). The CMOS process contributes minimal self-heating at 5 V, so thermal rise is dominated by package thermal resistance to ambient, typically well under 1 W even at full toggle activity. Always provide adequate PCB copper area for socketed ceramic packages.
When migrating the EP1810JC-35 footprint to the EP1810GC-35 (Gull-Wing) variant, the PCB land pattern is identical at 68 pads, but the lead-form differs: JC uses J-bend for through-hole/socket assembly while GC uses Gull-Wing for surface-mount soldering. According to Altera package drawings, both share a 1.27 mm pad pitch. Verify your PCB land pattern matches the IPC-7351 standard for CQCC-68 before switching lead-form, especially for high-vibration or thermal-cycling applications where Gull-Wing provides better solder-joint reliability.
Estimated: the EP1810JC-35's 5 V CMOS output drive is rated for typical TTL load compatibility (e.g. 4 mA IOL / -4 mA IOH per Altera datasheet). When driving long backplane traces or high-capacitive loads, add series-damping resistors near the output pins to control overshoot and ringing. For buses longer than 200 mm, use 33 ohm series resistors to match the typical 50-70 ohm trace impedance; for shorter board-internal traces, no series termination is required. The 35 ns propagation delay budget includes typical output rise/fall times of 3-5 ns at 50 pF load.
Informations de conformité
RoHS compliant and lead-free per Altera-Price distributor listing. REACH, halogen-free, and conflict-minerals status not explicitly listed in the verified web data and marked unknown. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. For automotive or industrial applications, consider MAX V CPLD family with explicit automotive qualification.
