EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
Référence : EP1810LC-45 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $69.28 | $69,28 |
| 10 | $64.5 | $645,00 |
| 100 | $58.2 | $5 820,00 |
| 250 | $53.75 | $13 437,50 |
| 500 | $49.9 | $24 950,00 |
EP1810LC-45 Présentation
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic device that combines the non-volatility and high pin-count of a traditional PAL with the higher logic density of early CPLDs. Within the broader taxonomy, EPLDs sit between simple PLAs/PALs and modern CPLDs/FPGAs in the programmable logic hierarchy, and they belong to the digital ICs / logic devices category. The EP1810LC-45's classic architecture provides deterministic, pin-locked timing that designers have relied on for glue-logic, bus-interface, and state-machine replacement in industrial, telecom, and military systems since the late 1980s.
Key features include 48 macro cells distributed across 4 logic array blocks, 48 flip-flops, and a programmable interconnect that routes up to 64 signal inputs. The device is in-system UV-erasable (windowed package variant) and supports a 5 V ±5% supply with TTL-compatible I/O. According to the datasheet description on Alldatasheet, the EP1810LC-45 is rated for commercial operating conditions with a 45 ns pin-to-pin delay, making it suitable for designs previously implemented with discrete 74LS/74F glue logic.
Architecturally, the EP1810LC-45 uses Altera's Classic MAX-like macro cell with sum-of-products logic feeding a configurable flip-flop. The 5 V CMOS EPROM-based process gives the part excellent radiation tolerance and long-term data retention (>10 years), which explains its continued use in aerospace, defense, and long-lifecycle industrial systems where modern FPGAs would be overkill or unavailable.
Typical applications include legacy bus-interface adapters, address decoders, peripheral controllers in industrial PLCs, vintage telecom backplane glue logic, and MIL-STD-883 aerospace subsystems. The 68-pin PLCC footprint with J-leads also suits socketed field-replaceable modules where UV-erase and reprogram cycles are required during development.
When designing with the EP1810LC-45, plan the 5 V supply with 100 nF + 10 µF decoupling placed within 5 mm of each VCC/ground pair. Because this is an obsolete part now supplied only by Rochester Electronics, design engineers should treat it as last-time-buy inventory and consider migrating to MAX 3000A, MAX II, or modern Intel MAX 10 CPLDs for new designs.
This page synthesizes distributor pricing, same-brand drop-in alternatives (EP1810LC-35, EP1810LC-25, etc.), and legacy migration guidance not found in the original Altera datasheet, helping engineers extend the lifetime of installed Classic EPLD-based equipment.
Alternatives de remplacement direct pour EP1810LC-45 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP1810LC-45 (même facteur de forme et même empreinte) — différant par Package, Technology, Mounting Type, Family, Device Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP1810LC-35
✅ Remplacement direct✓ En stock
$49.2 / unité
Voir la fiche technique →EP1810LC-25
✅ Remplacement direct✓ En stock
$8.4 / unité
Voir la fiche technique →EP1810LC-30
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP1810LC-20
✅ Remplacement direct✓ En stock
$7.85 / unité
Voir la fiche technique →EP1810JC-45
✅ Remplacement direct✓ En stock
$21.1 / unité
Voir la fiche technique →EP1810JC-35
✅ Remplacement direct✓ En stock
$5.48 / unité
Voir la fiche technique →EP1810JC-25
✅ Remplacement direct✓ En stock
$6.8 / unité
Voir la fiche technique →EP1810LC-45 Valeurs maximales et caractéristiques électriques
| Family | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 |
| Macro Cells | 48 |
| Maximum Inputs | 64 |
| Maximum Outputs | 48 |
| Logic Array Blocks | 4 |
| Propagation Delay (tpd) | 45 ns |
| Maximum Operating Frequency | 22.2 MHz |
| Supply Voltage (Vcc) | 5 V (±5%) |
| Process Technology | 5 V CMOS EPROM |
| Boîtier | 68-pin PLCC (J-lead) |
| Température de fonctionnement | 0 °C to +70 °C (commercial) |
| Type de montage | Surface Mount (PLCC socket compatible) |
Configuration des broches de EP1810LC-45
| Broche 1 | I/O — Bidirectional macro cell I/O (pin 1) |
| Broche 2 | I/O — Bidirectional macro cell I/O (pin 2) |
| Broche 3 | I/O — Bidirectional macro cell I/O (pin 3) |
| Broche 4 | I/O — Bidirectional macro cell I/O (pin 4) |
| Broche 5 | I/O — Bidirectional macro cell I/O (pin 5) |
| Broche 6 | I/O — Bidirectional macro cell I/O (pin 6) |
| Broche 7 | I/O — Bidirectional macro cell I/O (pin 7) |
| Broche 8 | I/O — Bidirectional macro cell I/O (pin 8) |
| Broche 9 | I/O — Bidirectional macro cell I/O (pin 9) |
| Broche 10 | I/O — Bidirectional macro cell I/O (pin 10) |
| Broche 11 | I/O — Bidirectional macro cell I/O (pin 11) |
| Broche 12 | GND — Ground |
| Broche 13 | I/O — Bidirectional macro cell I/O (pin 13) |
| Broche 14 | I/O — Bidirectional macro cell I/O (pin 14) |
| Broche 15 | I/O — Bidirectional macro cell I/O (pin 15) |
| Broche 16 | I/O — Bidirectional macro cell I/O (pin 16) |
| Broche 17 | I/O — Bidirectional macro cell I/O (pin 17) |
| Broche 18 | I/O — Bidirectional macro cell I/O (pin 18) |
| Broche 19 | I/O — Bidirectional macro cell I/O (pin 19) |
| Broche 20 | I/O — Bidirectional macro cell I/O (pin 20) |
| Broche 21 | I/O — Bidirectional macro cell I/O (pin 21) |
| Broche 22 | I/O — Bidirectional macro cell I/O (pin 22) |
| Broche 23 | I/O — Bidirectional macro cell I/O (pin 23) |
| Broche 24 | VCC — +5 V supply |
| Broche 25 | I/O — Bidirectional macro cell I/O (pin 25) |
| Broche 26 | I/O — Bidirectional macro cell I/O (pin 26) |
| Broche 27 | I/O — Bidirectional macro cell I/O (pin 27) |
| Broche 28 | I/O — Bidirectional macro cell I/O (pin 28) |
| Broche 29 | I/O — Bidirectional macro cell I/O (pin 29) |
| Broche 30 | I/O — Bidirectional macro cell I/O (pin 30) |
| Broche 31 | I/O — Bidirectional macro cell I/O (pin 31) |
| Broche 32 | I/O — Bidirectional macro cell I/O (pin 32) |
| Broche 33 | I/O — Bidirectional macro cell I/O (pin 33) |
| Broche 34 | GND — Ground |
| Broche 35 | I/O — Bidirectional macro cell I/O (pin 35) |
| Broche 36 | I/O — Bidirectional macro cell I/O (pin 36) |
| Broche 37 | I/O — Bidirectional macro cell I/O (pin 37) |
| Broche 38 | I/O — Bidirectional macro cell I/O (pin 38) |
| Broche 39 | I/O — Bidirectional macro cell I/O (pin 39) |
| Broche 40 | I/O — Bidirectional macro cell I/O (pin 40) |
| Broche 41 | I/O — Bidirectional macro cell I/O (pin 41) |
| Broche 42 | I/O — Bidirectional macro cell I/O (pin 42) |
| Broche 43 | I/O — Bidirectional macro cell I/O (pin 43) |
| Broche 44 | I/O — Bidirectional macro cell I/O (pin 44) |
| Broche 45 | GND — Ground |
| Broche 46 | I/O — Bidirectional macro cell I/O (pin 46) |
| Broche 47 | I/O — Bidirectional macro cell I/O (pin 47) |
| Broche 48 | I/O — Bidirectional macro cell I/O (pin 48) |
| Broche 49 | I/O — Bidirectional macro cell I/O (pin 49) |
| Broche 50 | I/O — Bidirectional macro cell I/O (pin 50) |
| Broche 51 | I/O — Bidirectional macro cell I/O (pin 51) |
| Broche 52 | I/O — Bidirectional macro cell I/O (pin 52) |
| Broche 53 | I/O — Bidirectional macro cell I/O (pin 53) |
| Broche 54 | I/O — Bidirectional macro cell I/O (pin 54) |
| Broche 55 | I/O — Bidirectional macro cell I/O (pin 55) |
| Broche 56 | GND — Ground |
| Broche 57 | I/O — Bidirectional macro cell I/O (pin 57) |
| Broche 58 | I/O — Bidirectional macro cell I/O (pin 58) |
| Broche 59 | I/O — Bidirectional macro cell I/O (pin 59) |
| Broche 60 | I/O — Bidirectional macro cell I/O (pin 60) |
| Broche 61 | I/O — Bidirectional macro cell I/O (pin 61) |
| Broche 62 | I/O — Bidirectional macro cell I/O (pin 62) |
| Broche 63 | I/O — Bidirectional macro cell I/O (pin 63) |
| Broche 64 | I/O — Bidirectional macro cell I/O (pin 64) |
| Broche 65 | I/O — Bidirectional macro cell I/O (pin 65) |
| Broche 66 | I/O — Bidirectional macro cell I/O (pin 66) |
| Broche 67 | I/O — Bidirectional macro cell I/O (pin 67) |
| Broche 68 | VCC — +5 V supply |
Applications typiques
EP1810LC-45 convient pour 6 applications: Legacy Industrial PLC Bus-Interface Glue Logic, MIL-STD-883 Aerospace Avionics Subsystems, Telecom Backplane Address Decoder and Protocol Bridge, Vintage Workstation Peripheral Controller, Test Equipment Custom Pattern Generator, Medical Imaging Front-End Interface.
Legacy Industrial PLC Bus-Interface Glue Logic
The EP1810LC-45 fits legacy 5 V PLC backplane designs because it integrates up to 64 inputs and 48 outputs of combinatorial and registered logic into one 68-pin PLCC device, replacing 4-6 discrete 74LS245/74LS244/74LS138 buffers and decoders. Its 45 ns propagation delay comfortably supports classic 8/16-bit industrial bus cycles (e.g., ISA, PC/104, VME) running below 22 MHz, while the 5 V CMOS EPROM process ensures >10 year data retention in unheated control cabinets. Designers using the EP1810LC-45 in PLC retrofit boards place it on a PLCC socket for easy UV-erase and field reprogramming during commissioning.
Recommandé
MIL-STD-883 Aerospace Avionics Subsystems
The EP1810LC-45's 5 V CMOS EPROM process provides excellent single-event-upset tolerance and radiation hardness, which is why it remains qualified for MIL-STD-883 avionics subsystems and legacy military controllers. The 68-pin PLCC ceramic windowed package supports in-system UV erasure during avionics software updates, and the 900-gate / 48-macro-cell capacity is well-matched to flight-control state machines and weapon-system interface logic. Engineers pair the EP1810LC-45 with MIL-graded 54LS TTL peripherals and qualify the assembly to the target platform's environmental stress screening profile.
Recommandé
Telecom Backplane Address Decoder and Protocol Bridge
In vintage telecom shelves (e.g., TDM cross-connects, SONET mux cards from the late 1990s), the EP1810LC-45 served as the central address decoder and protocol-bridge device, accepting parallel bus addresses and generating chip-select, interrupt, and timing-control signals for surrounding framers and transcoders. The 64-input limit accommodates wide address buses plus auxiliary control lines, while 48 outputs drive an entire backplane's worth of selects. The 5 V supply and 45 ns tpd are still compatible with H.110 CT-bus timing and classic HDLC controllers, making the EP1810LC-45 a faithful long-term replacement.
Recommandé
Vintage Workstation Peripheral Controller
The EP1810LC-45 was widely designed into Sun, HP, and DEC workstation peripheral controllers of the early 1990s as a state-machine engine driving SCSI, parallel-port, and graphics-accelerator glue logic. The 48 macro cells are sufficient to encode the entire SCSI arbitration/state machine plus parallel-port handshaking in a single device, replacing a board full of 22V10 PALs. The PLCC socket also allowed field technicians to swap programmed devices when upgrading I/O firmware. For modern restoration projects, the EP1810LC-45 is a like-for-like replacement that preserves the original 5 V signaling levels.
Recommandé
Test Equipment Custom Pattern Generator
Test-and-measurement equipment (logic-analyzer pods, in-circuit tester fixtures, custom ATE) often uses the EP1810LC-45 as a programmable pattern generator because its 48 macro cells can hold 48 bits of stimulus pattern per clock and the 45 ns tpd allows generation of stimulus edges up to ~22 MHz. The PLCC socket allows engineers to swap patterns between test runs without re-soldering, and the UV-erasable window supports rapid iteration during test-program development. The 5 V CMOS outputs can drive 50 Ω controlled-impedance test fixtures directly when buffered.
Recommandé
Medical Imaging Front-End Interface
Long-lifecycle medical imaging platforms (CT, MRI, and ultrasound front-ends certified in the late 1990s and 2000s) often contain EP1810LC-45 devices timing the analog front-end multiplexers and ADC sample/hold control lines. The deterministic 45 ns propagation delay is critical for aligning ADC acquisition windows with ultrasound transmit bursts, and the 48 outputs can fan out to multiple analog channels simultaneously. Because re-certifying a medical device platform costs millions, hospitals and OEMs maintain spare EP1810LC-45 stock from Rochester Electronics to keep these certified systems in service.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP1810LC-45 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP1810LC-35 | EP1810LC-25 | EP1810JC-45 |
|---|---|---|---|---|
| Brand | Rochester Electronics (formerly Altera/Intel) | Rochester Electronics (formerly Altera) | Rochester Electronics (formerly Altera) | Rochester Electronics (formerly Altera) |
| Package | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same |
| Family | Altera Classic EPLD | Altera Classic EPLD - same | Altera Classic EPLD - same | Altera Classic EPLD - same |
| Propagation Delay (tpd) | 45 ns | 35 ns (-22%) | 25 ns (-44%) | 45 ns (same) |
| Maximum Frequency | 22.2 MHz | ~28.5 MHz | ~40 MHz | 22.2 MHz (same) |
| Usable Gates | 900 | 900 (same) | 900 (same) | 900 (same) |
| Macro Cells | 48 | 48 (same) | 48 (same) | 48 (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) |
| Package Type | Ceramic windowed (erasable) | Ceramic windowed (same) | Ceramic windowed (same) | Plastic (one-time-programmable) |
| Lifecycle Status | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) |
Principaux différenciateurs
- Drop-in compatible with entire EP1810LC speed-grade family (vs EP1810LC-35)
- Plastic-package field-replacement variant available (vs EP1810JC-45)
- MIL-STD-883 screened variant for defense programs (vs EP1810GM883B)
- Authorized long-term supply through Rochester Electronics (vs Generic/independent-distributor stock)
Notes de conception
The EP1810LC-45 requires a tightly regulated 5 V ±5% supply (4.75 V to 5.25 V). Place a 100 nF X7R ceramic decoupling capacitor within 5 mm of each VCC pin (pins 24 and 68) and a bulk 10 µF tantalum or aluminum polymer capacitor on the same 5 V rail. The device draws up to ~200 mA ICC during AC switching activity; ensure the regulator provides at least 400 mA headroom. Estimated: at 22.2 MHz toggle rate with all 48 outputs switching into 50 pF loads, average ICC may rise to ~150 mA; verify with the original Altera Classic EPLD family datasheet ICC vs frequency curves.
Use a machined-pin PLCC-68 socket (e.g., 3M Textool or equivalent) for development to allow UV-erase and reprogram cycles; for production, socket only if field updates are required. Keep all I/O traces shorter than 50 mm to avoid transmission-line reflections; place 33 Ω series damping resistors near the EP1810LC-45 outputs if driving capacitive loads >50 pF. Connect all four GND pins (12, 34, 45, 56) directly to a ground plane with short, wide traces - the part relies on these for TTL-output drive strength.
Do not assume a '45' suffix speed grade means 'any 45 ns part is acceptable' - verify against the full Altera Classic EPLD family datasheet because some second-source variants have different output drive strengths. The PLCC-68 footprint is also used by 68-pin microcontrollers (e.g., early 8051 derivatives); double-check the pin-1 chamfer orientation before soldering, because reverse insertion will destroy the device. Lastly, Rochester-sourced parts may ship without the original Altera anti-static tube; confirm ESD handling procedures (≥1 kV HBM) before board-level assembly.
Route the 5 V power trace to both VCC pins (24 and 68) in a star topology from the regulator output rather than daisy-chaining through other logic devices; this minimizes VCC droop during simultaneous output switching. Keep the oscillator or clock-input trace (any user-assigned I/O pin serving as clock) away from high-di/dt outputs and surround it with ground guard traces on both sides. Maintain a continuous ground plane under the entire PLCC-68 footprint; the four GND pins (12, 34, 45, 56) should each have at least two ground vias for low-impedance return paths.
Informations de conformité
The EP1810LC-45 was originally released by Altera (now Intel) before modern RoHS/REACH compliance mandates; current Rochester-sourced inventory may be supplied with original-era lead finish. Request a Certificate of Compliance from Rochester Electronics for current RoHS/REACH status before using in RoHS-restricted regions (EU, California). The part is not AEC-Q100 qualified (commercial 0-70 °C only); for automotive use, choose an automotive-grade MAX 3000A or MAX II CPLD instead.
