EP1810LI-45 vs EP1810JI-35 Comparaison
Comparaison détaillée côte à côte de EP1810LI-45 par Rochester Electronics et EP1810JI-35 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ Actif
Comparaison des spécifications
| Paramètre | EP1810LI-45 | EP1810JI-35 |
|---|---|---|
| Marque | Rochester Electronics | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $64,10 | $18,60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | — |
| Tension d'alimentation | 5 V | 5 V (typical classic EPLD) |
| Plage de température de fonctionnement | -40 C to +85 C (Industrial, 'I' suffix) | — |
| Boîtier | 68-pin PLCC / PQCC68 (J-Lead) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | — |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Température de fonctionnement | — | -40C to +85C (Industrial) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Type de montage | — | Through-Hole (J-lead) |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |