EP1810LI-45 vs EP1810JI-35 对比
详细并排对比 EP1810LI-45 出自 Rochester Electronics 和 EP1810JI-35 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ 量产中
规格对比
| 参数 | EP1810LI-45 | EP1810JI-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $64.10 | $18.60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | — |
| 电源电压 | 5 V | 5 V (typical classic EPLD) |
| 工作温度范围 | -40 C to +85 C (Industrial, 'I' suffix) | — |
| 封装 | 68-pin PLCC / PQCC68 (J-Lead) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | — |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| 工作温度 | — | -40C to +85C (Industrial) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| 安装类型 | — | Through-Hole (J-lead) |
| MSL 等级 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |