EP1810LI-45 vs EP1810JI-35 비교

다음의 상세 나란히 비교: EP1810LI-45 제조: Rochester Electronics 및 EP1810JI-35 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810LI-45 EP1810JI-35
브랜드 Rochester Electronics Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $64.10 $18.60
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic —
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration —
공급 전압 5 V 5 V (typical classic EPLD)
동작 온도 범위 -40 C to +85 C (Industrial, 'I' suffix) —
패키지 68-pin PLCC / PQCC68 (J-Lead) 28-pin JLCC (J-leaded ceramic, windowed)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
RoHS 상태 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) —
Device Family — Classic EPLD
Logic Array Blocks — 8 LABs of 16 macrocells
Dedicated Inputs — 48
Pin-to-Pin Propagation Delay (tPD) — 35 ns
Speed Grade — -35
Process Technology — CMOS EPROM (UV-erasable)
동작 온도 — -40C to +85C (Industrial)
Programmability — UV-erase, windowed for lab reprogram
실장 유형 — Through-Hole (J-lead)
MSL 레벨 — [DATA_NEEDED: MSL rating]
Programming Interface — JEDEC fuse file via legacy programmer

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