EP1K100QI208-2N vs EP1K100QI208-2 Comparaison
Comparaison détaillée côte à côte de EP1K100QI208-2N par Altera et EP1K100QI208-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1K100QI208-2N | EP1K100QI208-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $23,90 |
| Series | ACEX-1K | — |
| FPGA Family | ACEX-1K | — |
| Number of Logic Elements/Cells | 4992 | — |
| Number of LABs/CLBs | 624 | — |
| Total RAM Bits | 49152 | — |
| Number of User I/O | 147 | — |
| Boîtier / Format | 208-BFQFP | — |
| Type de montage | Surface Mount | Surface Mount |
| Core Supply Voltage | 2.5 V | — |
| Speed Grade | -2 | — |
| Temperature Grade | I (industrial) | — |
| System Gates | 257000 | 100,000 |
| Typical Gate Count | 100K gates (family) | — |
| Plage de température de fonctionnement | [DATA_NEEDED: exact industrial temperature limits from ACEX-1K datasheet] | — |
| Max User I/O in 208-BFQFP | 147 | — |
| Total Number of Configuration Bits | [DATA_NEEDED: configuration bitstream size] | — |
| Maximum Internal Clock Frequency | [DATA_NEEDED: clock frequency for -2 speed grade] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| PLL/Clock Management | [DATA_NEEDED: PLL availability on EP1K100] | — |
| Statut RoHS | [DATA_NEEDED: manufacturer RoHS certificate] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | ACEX-1K |
| Logic Elements | — | 4,992 cells |
| Logic Array Blocks (LABs) | — | 624 |
| Embedded Memory (EAB) | — | 49,152 bits |
| User I/Os | — | 147 |
| Maximum Operating Frequency | — | 250 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| Process Technology | — | 0.22 umm CMOS SRAM |
| Boîtier | — | 208-pin PQFP (BFQFP) |
| Pitch | — | 0.5 mm |
| Température de fonctionnement | — | -40C to +85C (Industrial) |
| Configuration Interface | — | JTAG (IEEE 1149.1) / serial / EPC2 |
| Global Clock Networks | — | 4 |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, 5V tolerant |