EP1K100QI208-2N vs EP1K100QI208-2 比較
詳細な並列比較: EP1K100QI208-2N メーカー: Altera および EP1K100QI208-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K100QI208-2N | EP1K100QI208-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $23.90 |
| Series | ACEX-1K | — |
| FPGA Family | ACEX-1K | — |
| Number of Logic Elements/Cells | 4992 | — |
| Number of LABs/CLBs | 624 | — |
| Total RAM Bits | 49152 | — |
| Number of User I/O | 147 | — |
| パッケージ / ケース | 208-BFQFP | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Core Supply Voltage | 2.5 V | — |
| Speed Grade | -2 | — |
| Temperature Grade | I (industrial) | — |
| System Gates | 257000 | 100,000 |
| Typical Gate Count | 100K gates (family) | — |
| 動作温度範囲 | [DATA_NEEDED: exact industrial temperature limits from ACEX-1K datasheet] | — |
| Max User I/O in 208-BFQFP | 147 | — |
| Total Number of Configuration Bits | [DATA_NEEDED: configuration bitstream size] | — |
| Maximum Internal Clock Frequency | [DATA_NEEDED: clock frequency for -2 speed grade] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| PLL/Clock Management | [DATA_NEEDED: PLL availability on EP1K100] | — |
| RoHS ステータス | [DATA_NEEDED: manufacturer RoHS certificate] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | ACEX-1K |
| Logic Elements | — | 4,992 cells |
| Logic Array Blocks (LABs) | — | 624 |
| Embedded Memory (EAB) | — | 49,152 bits |
| User I/Os | — | 147 |
| Maximum Operating Frequency | — | 250 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| Process Technology | — | 0.22 umm CMOS SRAM |
| パッケージ | — | 208-pin PQFP (BFQFP) |
| Pitch | — | 0.5 mm |
| 動作温度 | — | -40C to +85C (Industrial) |
| Configuration Interface | — | JTAG (IEEE 1149.1) / serial / EPC2 |
| Global Clock Networks | — | 4 |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, 5V tolerant |