EP1K30TC144-2 vs EP1K30TI144-2N Comparaison
Comparaison détaillée côte à côte de EP1K30TC144-2 par Intel et EP1K30TI144-2N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1K30TC144-2 | EP1K30TI144-2N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,40 | $25,00 |
| Family | ACEX 1K | — |
| Logic Elements / Cells | 1,728 | 1728 |
| System Gates | 30,000 | — |
| Logic Array Blocks (LABs) | 216 | — |
| User I/Os | 102 | — |
| Embedded Array Blocks (EABs) | 6 | — |
| Total EAB Memory | 24,576 bits | — |
| Process Technology | 0.22 µm SRAM LUT | 0.22 µm CMOS SRAM |
| Core Supply Voltage (VCCINT) | 2.5 V (2.375 V - 2.625 V) | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (LVTTL/LVCMOS), 2.5 V, or PCI | — |
| Maximum Internal Clock Frequency | 200 MHz | — |
| Boîtier | 144-pin TQFP (TC) | 144-pin LQFP |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Configuration Method | Passive Serial / JTAG / EPC1/EPC2 PROM | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (per Utmel product note) |
| Speed Grade | -2 (mid commercial speed grade) | -2 |
| Series | — | ACEX-1K |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gate Count | — | 30,000 gates |
| Embedded Memory (RAM bits) | — | 24,576 bits |
| Maximum User I/O | — | 102 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count] |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V |
| Operating Temperature Grade | — | Industrial |
| Plage de température de fonctionnement | — | -40 °C to +100 °C ambient |
| Lead Pitch | — | 0.5 mm |
| Configuration Interface | — | JTAG (IEEE 1149.1), serial passive/active |