EP1M120B484C5 vs EP1M120B484C8A Comparaison
Comparaison détaillée côte à côte de EP1M120B484C5 par Intel et EP1M120B484C8A par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120B484C5 | EP1M120B484C8A |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $65,00 | $62,00 |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements | 4,800 | — |
| Typical Gates | 120,000 | — |
| Maximum User I/O | 303 | [DATA_NEEDED: user I/O count] |
| Boîtier | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) | 484-ball FineLine BGA |
| Température de fonctionnement | 0C to +85C (commercial) | [DATA_NEEDED: full range] |
| Speed Grade | 5 (slowest) | 8 |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.18 um CMOS | — |
| PLLs | 4 | — |
| Embedded RAM Bits | 49,152 | — |
| True LVDS Channels | Up to 34 pairs | — |
| Maximum LVDS Data Rate | 840 Mbps per channel | — |
| Configuration Scheme | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG | — |
| Peak Reflow Temperature | 220 C | 220 C (per JEDEC J-STD-020) |
| Lead-Free / RoHS | SnPb ball finish (non-RoHS by default) | — |
| Multipliers | Embedded in system blocks for DSP | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Logic Elements (approx.) | — | 120 |
| Nombre de broches | — | 484 |
| Temperature Grade | — | Commercial (C) |
| Logic Blocks | — | [DATA_NEEDED: LAB count] |
| Embedded Memory | — | [DATA_NEEDED: RAM bits] |
| Supply Voltage Core | — | [DATA_NEEDED: VCCINT] |
| Supply Voltage I/O | — | [DATA_NEEDED: VCCIO] |
| Configuration Method | — | [DATA_NEEDED: SRAM/serial/etc.] |
| Statut RoHS | — | [DATA_NEEDED: check distributor] |
| Niveau MSL | — | [DATA_NEEDED: per JEDEC J-STD-020] |