EP1M350F780C6N vs EP1M350F780C8 Comparaison
Comparaison détaillée côte à côte de EP1M350F780C6N par Intel et EP1M350F780C8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1M350F780C6N | EP1M350F780C8 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $219,40 | $175,00 |
| Family | Mercury (EP1M350) | — |
| Device Type | Loadable Programmable Logic Device (PLD) / FPGA | — |
| Logic Family | CMOS, SRAM-based LUT | — |
| System Gates | 350,000 | — |
| Logic Cells / Elements | 14,400 | — |
| User I/Os | 486 | — |
| Integrated Transceivers | Yes, with CDR up to 1.25 Gbps | — |
| Core Supply Voltage | 1.8 V | — |
| Boîtier | 780-ball FC-FBGA (FINE LINE BGA-780) | 780-ball FineLine BGA |
| Terminal Form | Ball | — |
| Package Code (JEDEC) | S-PBGA-B780 | — |
| Température de fonctionnement | 0 C to 85 C | 0C to +85C (commercial) |
| Configuration Interface | JTAG (IEEE 1149.1) / passive serial | IEEE 1532 / passive serial / JTAG |
| Statut RoHS | [DATA_NEEDED: rohs_status] | unknown (legacy device) |
| Niveau MSL | [DATA_NEEDED: msl_level] | [DATA_NEEDED: MSL rating] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| Architecture | Look-up table (LUT)-based, optimized for high-speed serial I/O | — |
| Total Package Pins / Balls | 780 | — |
| Device Family | — | Altera APEX Mercury (EP1M) |
| Typical Gates | — | 350,000 |
| Maximum Logic Elements (LEs) | — | 12,160 |
| Embedded RAM Blocks | — | 4 dual-port RAM blocks |
| Speed Grade | — | C8 (commercial, speed bin 8) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards) |
| Global Clock Networks | — | 8 |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |
| In-System Programmability | — | Yes (ISP via JTAG) |
| Type de montage | — | Surface Mount (BGA) |