EP1S20F672C7N vs EP1S20F672I7 Comparaison
Comparaison détaillée côte à côte de EP1S20F672C7N par Intel et EP1S20F672I7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1S20F672C7N | EP1S20F672I7 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $109,20 | $199,50 |
| Series | Stratix (first generation) | — |
| Family | Stratix | Stratix (first generation) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Cells | 18,460 | — |
| Configurable Logic Blocks (CLBs) | 2,132 | — |
| Embedded Memory (TriMatrix) | 1,669,248 bits (426 Kbit total) | — |
| DSP Blocks | 56 (dedicated 18x18 multipliers) | [DATA_NEEDED: exact DSP block count] |
| Maximum User I/O | 586 | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| PLLs | Up to 12 | — |
| Maximum Operating Frequency | 420.17 MHz | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | — |
| Boîtier | 672-FBGA (FineLine BGA) | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Package Body Size | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Température de fonctionnement | 0°C to +85°C (commercial) | -40C to +85C (industrial grade, I7 suffix) |
| Speed Grade | C7 (-7) | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Lead-Free / RoHS | Yes (lead-free finish, RoHS compliant) | — |
| Configuration Modes | PS, PPS, FPP, JTAG | Passive Serial, Passive Parallel, JTAG |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | unknown |
| Maximum RAM Bits | — | 1,669,248 |
| Maximum User I/Os | — | 426 |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Logic Family | — | CMOS |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Statut RoHS | — | unknown |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| Status | — | Last Time Buy (per distributor notices) |