EP1S80B956C6AB vs EP1S80B956C5N Comparaison
Comparaison détaillée côte à côte de EP1S80B956C6AB par Intel et EP1S80B956C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S80B956C6AB | EP1S80B956C5N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $142,00 | $175,00 |
| Family | Stratix | Altera Stratix |
| Logic Elements (LEs) | 79,040 | — |
| Logic Cells | 79,040 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 450.05 MHz | — |
| User I/O Pins | 683 | — |
| Boîtier | 956-ball FCBGA | 956-ball FCBGA |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial, 'C' grade) |
| Memory Blocks | TriMatrix embedded RAM | — |
| DSP Blocks | Embedded DSP blocks (per Stratix family) | Yes (dedicated hardware multipliers) |
| PLLs | Multiple PLLs for clock management | Yes (multiple) |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | — | 79,040 |
| Maximum Internal Clock Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V |
| Speed Grade | — | 5 |
| Memory Architecture | — | TriMatrix on-chip memory |
| I/O Standard Support | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per Stratix family) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |