EP1S80B956C6AB vs EP1S80B956C5N 对比
详细并排对比 EP1S80B956C6AB 出自 Intel 和 EP1S80B956C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S80B956C6AB | EP1S80B956C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $142.00 | $175.00 |
| Family | Stratix | Altera Stratix |
| Logic Elements (LEs) | 79,040 | — |
| Logic Cells | 79,040 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 450.05 MHz | — |
| User I/O Pins | 683 | — |
| 封装 | 956-ball FCBGA | 956-ball FCBGA |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | Compliant | [DATA_NEEDED: RoHS status] |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial, 'C' grade) |
| Memory Blocks | TriMatrix embedded RAM | — |
| DSP Blocks | Embedded DSP blocks (per Stratix family) | Yes (dedicated hardware multipliers) |
| PLLs | Multiple PLLs for clock management | Yes (multiple) |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | — | 79,040 |
| Maximum Internal Clock Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V |
| Speed Grade | — | 5 |
| Memory Architecture | — | TriMatrix on-chip memory |
| I/O Standard Support | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per Stratix family) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |