EP1S80B956C6AB vs EP1S80B956C6 Comparaison
Comparaison détaillée côte à côte de EP1S80B956C6AB par Intel et EP1S80B956C6 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S80B956C6AB | EP1S80B956C6 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $142,00 | $1 000,00 |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 79,040 | — |
| Logic Cells | 79,040 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 450.05 MHz | — |
| User I/O Pins | 683 | — |
| Boîtier | 956-ball FCBGA | 956-BBGA, FCBGA, 40x40 mm |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to 85C (TJ, commercial) |
| Memory Blocks | TriMatrix embedded RAM | — |
| DSP Blocks | Embedded DSP blocks (per Stratix family) | 22 |
| PLLs | Multiple PLLs for clock management | — |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LE) | — | 79,040 |
| Logic Array Blocks (LAB) | — | 7,904 |
| Total Memory Bits | — | 7,427,520 (TriMatrix: M512 + M4K + M-RAM) |
| Embedded Memory | — | 6.336 Mbit |
| Maximum User I/O | — | 683 |
| Supply Voltage - Core | — | 1.425 V to 1.575 V |
| Speed Grade | — | -6 |
| Maximum Transceiver Rate | — | [DATA_NEEDED: high-speed transceiver data rate, GHz] |