EP1SGX25FF1020I5N vs EP1SGX25FF1020I7 Comparaison
Comparaison détaillée côte à côte de EP1SGX25FF1020I5N par Altera et EP1SGX25FF1020I7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1SGX25FF1020I5N - Stratix GX FPGA, 25,660 LEs, FBGA-1020 | Altera
EP1SGX25FF1020I5N ⚠ Dernier achatAltera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 ObsoleteComparaison des spécifications
| Paramètre | EP1SGX25FF1020I5N | EP1SGX25FF1020I7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 050,00 | $210,00 |
| Family | Stratix GX | Stratix GX |
| Series | EP1SGX25 | EP1SGX25 |
| Logic Elements (LEs) | 25,660 | — |
| Configurable Logic Blocks (CLBs) | 2,566 | 2,566 |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Maximum Operating Frequency | [DATA_NEEDED: datasheet fmax value] | — |
| Operating Temperature Grade | Industrial (I) | — |
| Plage de température de fonctionnement | 0 C to 85 C (per digchip listing) | — |
| Boîtier | FBGA-1020 (33 x 33 mm, 1.00 mm pitch) | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Ball Count | 1020 | — |
| Terminal Pitch | 1.00 mm | [DATA_NEEDED: terminal pitch] |
| Type de montage | Surface Mount (BGA) | Surface Mount (FC-FBGA) |
| Lead-Free Finish | Yes (lead-free, per digchip) | — |
| Logic Family | CMOS | — |
| Statut RoHS | Compliant (per digchip) | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | 5 | 7 (highest production grade) |
| Logic Cells | — | 25,660 |
| Number of Terminals / Balls | — | 1020 |
| Terminal Form | — | Ball |
| Temperature Grade (suffix 'I') | — | Industrial |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Embedded Transceivers | — | Yes (Stratix GX feature) |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |