EP1SGX25FF1020I5N vs EP1SGX25FF1020I7 对比

详细并排对比 EP1SGX25FF1020I5N 出自 Altera 和 EP1SGX25FF1020I7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1SGX25FF1020I5N EP1SGX25FF1020I5N - Stratix GX FPGA, 25,660 LEs, FBGA-1020 | Altera

EP1SGX25FF1020I5N - Stratix GX FPGA, 25,660 LEs, FBGA-1020 | Altera

EP1SGX25FF1020I5N ⚠ 最后一次采购

规格对比

参数 EP1SGX25FF1020I5N EP1SGX25FF1020I7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $2,050.00 $210.00
Family Stratix GX Stratix GX
Series EP1SGX25 EP1SGX25
Logic Elements (LEs) 25,660 —
Configurable Logic Blocks (CLBs) 2,566 2,566
Process Technology 130 nm CMOS 130 nm CMOS
Core Supply Voltage 1.5 V 1.5 V
Maximum Operating Frequency [DATA_NEEDED: datasheet fmax value] —
Operating Temperature Grade Industrial (I) —
工作温度范围 0 C to 85 C (per digchip listing) —
封装 FBGA-1020 (33 x 33 mm, 1.00 mm pitch) FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Ball Count 1020 —
Terminal Pitch 1.00 mm [DATA_NEEDED: terminal pitch]
安装类型 Surface Mount (BGA) Surface Mount (FC-FBGA)
Lead-Free Finish Yes (lead-free, per digchip) —
Logic Family CMOS —
RoHS 状态 Compliant (per digchip) [DATA_NEEDED: RoHS compliance]
Speed Grade 5 7 (highest production grade)
Logic Cells — 25,660
Number of Terminals / Balls — 1020
Terminal Form — Ball
Temperature Grade (suffix 'I') — Industrial
Combinatorial Delay per CLB — 9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant — [DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency — [DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers — Yes (Stratix GX feature)
Configuration Method — SRAM-based (volatile, requires configuration at power-up)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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