EP20K200RC208-3N vs EP20K200RC208-1X Comparaison
Comparaison détaillée côte à côte de EP20K200RC208-3N par Altera et EP20K200RC208-1X par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K200RC208-3N - APEX 20K FPGA 200K Gates 8320 Cells 167MHz | Altera
EP20K200RC208-3N Obsolete
Comparaison des spécifications
| Paramètre | EP20K200RC208-3N | EP20K200RC208-1X |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $39,00 | $35,80 |
| Family | APEX-20K | APEX-20KE |
| Series | APEX 20K | — |
| Logic Elements | 8320 cells | 8,320 cells |
| System Gates | 200,000 | — |
| Embedded Memory | 106,496 bits | — |
| Maximum Operating Frequency | 167 MHz | — |
| User I/O Pins | 144 | — |
| Dedicated Inputs | 4 | — |
| Process Technology | 0.22 um CMOS | 0.18 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Standard Support | LVDS, 1.8V APEX-20KE family | — |
| Package Type | 208-RQFP / BFQFP with exposed pad | — |
| Terminal Pitch | 0.5 mm | — |
| Plage de température de fonctionnement | 0C to +85C (industrial) | — |
| Propagation Delay | 3.6 ns | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Type de montage | Surface Mount | Surface Mount (gull-wing leads) |
| Typical Gate Count | — | 200,000 gates |
| Embedded RAM Bits | — | 106,496 bits |
| Embedded RAM Blocks (ESBs) | — | 4 lanes / 52 ESBs |
| Maximum User I/O Pins | — | 144 (PQFP-208 variant) |
| Core Voltage | — | 1.8 V (±5%) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS, GTL+ |
| Speed Grade | — | -1X (1.8 V core, PQFP-208 pinout) |
| Boîtier | — | 208-pin PQFP / RQFP (28x28 mm), 0.5 mm pitch |
| Température de fonctionnement | — | 0 °C to +85 °C (commercial) |
| Configuration Interface | — | IEEE 1149.1 JTAG, serial, passive parallel (PPA), EPC configuration devices |
| MultiCore Architecture | — | LUT logic + product-term logic + embedded memory |
| PLL Count | — | 4 enhanced PLLs (with programmable phase shift) |
| Statut RoHS | — | Compliant (lead-free PQFP package) |
| Moisture Sensitivity Level | — | MSL 3 (per JEDEC J-STD-020, applicable to PQFP) |