EP20K400CB652C9ES vs EP20K400CB652I7 Comparaison
Comparaison détaillée côte à côte de EP20K400CB652C9ES par Intel et EP20K400CB652I7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400CB652C9ES | EP20K400CB652I7 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $149,50 |
| Series | APEX 20KC | — |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Embedded Memory (Bits) | 212992 | — |
| Number of User I/O | 488 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Number of Logic Array Blocks | 1040 | — |
| Maximum Operating Frequency | 250 MHz | 375.94 MHz |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Plage de température de fonctionnement | 0°C to +85°C (Commercial) | — |
| Type de montage | Surface Mount | — |
| Boîtier / Format | 652-BGA | — |
| Niveau MSL | 3 (168 Hours) | — |
| Packaging | Tray | — |
| Programmability Type | In-system programmable (SRAM-based) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PLL | Yes (4-phase) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (JESD-609 e0, contains lead) |
| Device Family | — | Field-Programmable Gate Array (FPGA) |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Core Supply Voltage | — | 1.8 V |
| I/O Supply Voltage | — | 1.8 V / 3.3 V |
| Boîtier | — | BGA-652 (652-ball) |
| Package Code (JESD-30) | — | S-PBGA-B652 |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O] |
| Embedded Memory | — | Embedded System Blocks (ESB) - dual-port RAM / FIFO / CAM |
| Configuration Method | — | SRAM + JTAG (ISP) |
| Speed Grade | — | 7 |
| Temperature Grade | — | Industrial (-40 °C to +100 °C) |
| Manufacturer Status | — | Obsolete (Intel/Altera legacy FPGA) |