EP20K400GC655-2 vs EP20K400GC655-2N Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2 par Altera et EP20K400GC655-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GC655-2 | EP20K400GC655-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $80,00 | $127,50 |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212992 |
| Maximum Internal Frequency | 200 MHz | — |
| Speed Grade | -2 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | — |
| LVDS Support | Yes | Yes |
| PLLs | 4 | — |
| Nombre de broches | 655 | — |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| Type de montage | Through-Hole (CPGA) | Through-Hole (CPGA, socket-compatible) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | Industrial (per Altera part-number -N suffix) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Boîtier / Format | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | — | JTAG / Passive Serial |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |