EP20K400GI655-1 vs EP20K400GC655-2 Comparaison
Comparaison détaillée côte à côte de EP20K400GI655-1 par Altera et EP20K400GC655-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GI655-1 | EP20K400GC655-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $80,00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | — |
| Logic Elements | 16640 | — |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | — |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | 655-BCPGA (CPGA-655) |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Température de fonctionnement | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Series | — | APEX-20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| System Gates | — | 400,000 |
| Logic Cells / Elements | — | 16,640 |
| Total RAM Bits | — | 212,992 |
| Maximum Internal Frequency | — | 200 MHz |
| Speed Grade | — | -2 |
| Process Technology | — | 0.22 µm CMOS |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 1.71 V to 1.89 V (MultiVolt) |
| LVDS Support | — | Yes |
| PLLs | — | 4 |
| Nombre de broches | — | 655 |
| Package Dimensions | — | 62.48 x 62.48 mm |
| Type de montage | — | Through-Hole (CPGA) |