EP20K600CF672C8N vs EP20K600CF672C7N Comparaison
Comparaison détaillée côte à côte de EP20K600CF672C8N par Intel et EP20K600CF672C7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672C8N | EP20K600CF672C7N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $108,00 | $108,00 |
| Device Type | SPLD | — |
| Product Type | FPGA / programmable logic device | — |
| Family | APEX 20KC | — |
| Nominal Gate Capacity | 600K gates | — |
| Logic Elements or Cells | 24,320 | — |
| Macros | 2,432 | — |
| User I/O Count | 508 | — |
| Package Terminals | 652 pins | — |
| Boîtier | BGA-652, 45 x 45 mm, 1.27 mm pitch | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch |
| Package Description | 672-pin FC-FBGA | — |
| Tension d'alimentation | 1.8 V | — |
| Listed Frequency | 301.21 MHz | — |
| Propagation Delay | 1.48 ns | 1.48 ns |
| Fabrication Process | 0.15 µm | — |
| Température de fonctionnement | 0°C to 85°C | 0 °C to +85 °C (Commercial) |
| Interconnect Metal | All-layer copper metal | — |
| I/O Configuration | 508 user I/O | — |
| Type de montage | Surface mount | Surface Mount (BGA) |
| Statut RoHS | unknown | unknown |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Configuration Method | [DATA_NEEDED: configuration memory and programming method] | — |
| Core Current | [DATA_NEEDED: core supply current] | — |
| I/O Bank Voltage | [DATA_NEEDED: supported I/O voltage range] | — |
| Junction Temperature | [DATA_NEEDED: maximum junction temperature] | — |
| Résistance thermique | [DATA_NEEDED: junction-to-ambient thermal resistance] | — |
| Device Family | — | APEX 20KC |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 600,000 |
| Logic Elements / Cells | — | 24,320 |
| Maximum User I/O Pins | — | 488 |
| Total Package Pins | — | 652 |
| Core Voltage | — | 1.8 V |
| Maximum Operating Frequency | — | 375.94 MHz |
| Process Technology | — | 0.15 µm all-layer copper-metal CMOS |
| Architecture | — | MultiCore (LUT + Embedded System Memory) |
| Speed Grade | — | C7 |
| Seated Height | — | 3.50 mm |