EP20K600CF672I9 vs EP20K600CF672C9 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672I9 par Intel et EP20K600CF672C9 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672I9 | EP20K600CF672C9 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $152,00 | $171,00 |
| Family | APEX 20KC | — |
| Logic Elements / Cells | 24,320 | — |
| System Gates | 600,000 | — |
| Maximum Operating Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper-metal |
| Core Voltage | 1.8 V | 1.8 V |
| Boîtier | 672-pin FC-FBGA | — |
| Type de montage | Surface Mount (BGA) | — |
| Temperature Grade | Industrial (-40°C to +85°C) | — |
| Speed Grade | 9 (fastest bin) | — |
| User I/O Pins | 311 (max) | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded Memory | [DATA_NEEDED: total RAM bits] | — |
| PLLs | Up to 4 | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS | — |
| Configuration Mode | Passive Serial / JTAG | — |
| Maximum Seated Height | 2.1 mm | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Device Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Maximum User I/O | — | 488 pins |
| Embedded Memory (EAB) | — | 311 Kbits |
| Propagation Delay | — | 1.48 ns |
| Maximum Internal Frequency | — | 250 MHz |
| Package Type | — | 672-pin FC-FBGA |
| Package Dimensions | — | 45 x 45 mm, 1.27 mm pitch |
| Total Pin Count | — | 652 balls |
| Température de fonctionnement | — | 0 °C to +85 °C (commercial) |
| Configuration Interface | — | IEEE 1149.1 JTAG / passive serial / EPC configuration |