EP2A25F672C7N vs EP2A25F672I6 Comparaison
Comparaison détaillée côte à côte de EP2A25F672C7N par Altera et EP2A25F672I6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672C7N | EP2A25F672I6 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $178,00 |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 cells | — |
| System Gates | Approximately 900,000 | — |
| User I/Os | 492 | — |
| Propagation Delay (tPD) | 1.69 ns | — |
| Internal Operating Frequency | Up to 500 MHz | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.18 µm CMOS |
| Logic Family | CMOS | — |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | — |
| Package Body Size | 27 x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Température de fonctionnement | 0 °C to 85 °C (commercial) | — |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Programmable Logic Type | Loadable PLD (in-system programmable) | — |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | Embedded System Blocks (ESB), dual-port RAM / CAM |
| PLLs | Up to 4 | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements (typical gates) | — | 25,000 |
| Fabric Architecture | — | SRAM-based LUT |
| Boîtier | — | 672-ball FineLine BGA (FBGA-672) |
| Core Voltage | — | 1.5 V |
| Configuration Method | — | External SRAM configuration device (EPC series) |
| Temperature Grade | — | Industrial (-40 °C to +100 °C ambient) |
| Speed Grade | — | 6 |
| DSP Blocks | — | MultiCore dedicated multipliers |
| Boundary Scan | — | JTAG (IEEE 1149.1) compliant |
| Clock Management | — | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | — | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Niveau MSL | — | [DATA_NEEDED: moisture sensitivity level] |