EP2A25F672C7N vs EP2A25F672I6 对比

详细并排对比 EP2A25F672C7N 出自 Altera 和 EP2A25F672I6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C7N EP2A25F672I6
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $195.00 $178.00
Family APEX II APEX II
Logic Elements 24,320 cells —
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.18 µm CMOS
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
工作温度 0 °C to 85 °C (commercial) —
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM Embedded System Blocks (ESB), dual-port RAM / CAM
PLLs Up to 4 —
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
封装 — 672-ball FineLine BGA (FBGA-672)
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
Speed Grade — 6
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等级 — [DATA_NEEDED: moisture sensitivity level]

数据手册与资源

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