EP2A25F672C7N vs EP2A25F672I6 비교

다음의 상세 나란히 비교: EP2A25F672C7N 제조: Altera 및 EP2A25F672I6 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP2A25F672C7N EP2A25F672I6
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $195.00 $178.00
Family APEX II APEX II
Logic Elements 24,320 cells —
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.18 µm CMOS
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
동작 온도 0 °C to 85 °C (commercial) —
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM Embedded System Blocks (ESB), dual-port RAM / CAM
PLLs Up to 4 —
실장 유형 Surface Mount Surface Mount (BGA)
RoHS 상태 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
패키지 — 672-ball FineLine BGA (FBGA-672)
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
Speed Grade — 6
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 레벨 — [DATA_NEEDED: moisture sensitivity level]

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