EP2A25F672I7N vs EP2A25F672I-9 Comparaison
Comparaison détaillée côte à côte de EP2A25F672I7N par Intel et EP2A25F672I-9 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672I7N | EP2A25F672I-9 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $175,00 | $195,00 |
| Family | APEX II | APEX II |
| Logic Elements (Cells) | 24,320 | — |
| Typical Gate Count | 900,000 | — |
| Maximum Internal Frequency | 500 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Boîtier | 672-ball FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Pin/Ball Count | 672 | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (I) | Industrial (-40 °C to +100 °C junction) |
| Speed Grade | 7 | -9 |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel | — |
| Design Software | Quartus II | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Statut du cycle de vie | Not Recommended for New Designs (NRND) | — |
| Logic Elements (typical) | — | 25,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |