EP2A40F1020I8N vs EP2A40F1020I9N Comparaison
Comparaison détaillée côte à côte de EP2A40F1020I8N par Intel et EP2A40F1020I9N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F1020I8N | EP2A40F1020I9N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $125,40 | $165,00 |
| Family | APEX II (EP2A40) | APEX II |
| Logic Elements | 38,400 cells | — |
| System Gates | 1.5 M (typical) | 1,500,000 (1.5 M) |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS, up to 8 metal layers |
| Core Voltage | 1.5 V | — |
| Maximum Internal Frequency | 376 MHz | — |
| User I/O Count | 735 (maximum) | 735 bidirectional I/O |
| Boîtier | 1020-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (-40 C to +100 C) / 'I' suffix | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) |
| Speed Grade | 8 | — |
| Architecture | LUT-based with embedded system blocks (ESBs) | — |
| Configuration | SRAM-based, JTAG / passive serial / passive parallel | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Number of PLLs | [DATA_NEEDED: PLL count] | — |
| Total Embedded Memory | [DATA_NEEDED: embedded memory bits] | — |
| Device Logic Elements / Cells | — | 38,400 cells |
| Maximum Operating Frequency | — | 366 MHz |
| Core Supply Voltage | — | 1.5 V |
| High-Speed I/O Standards | — | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport |
| Embedded Memory | — | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) |
| Clock Management | — | PLLs (count [DATA_NEEDED: PLL count]) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG |
| Statut du cycle de vie | — | Obsolete (per distributor listings / Altera APEX II family EOL) |