EP2S30F672C4 vs EP2S30F672C5 Comparaison
Comparaison détaillée côte à côte de EP2S30F672C4 par Intel et EP2S30F672C5 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S30F672C4 | EP2S30F672C5 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $498,43 | $155,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix II | — |
| Logic Elements / Cells | 33,880 | — |
| Total RAM Bits | 1,369,728 | 1,369,728 |
| Number of I/O | 500 | — |
| Boîtier | 672-BBGA, FCBGA (27x27 mm) | 672-pin FC-FBGA (flip-chip) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Core Voltage - Supply | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Maximum Core Frequency (datasheet benchmark) | 711 MHz | — |
| Température de fonctionnement | 0C to +85C (commercial, 'C' speed grade) | — |
| Embedded DSP Blocks | 16 (Stratix II S30 tier) | — |
| Number of PLLs | [DATA_NEEDED: PLL count for S30 tier] | — |
| Number of Global Clock Networks | [DATA_NEEDED: global clock network count] | — |
| Statut RoHS | Compliant | [DATA_NEEDED: confirmed RoHS compliance] |
| Lead-Free | Yes | — |
| Family | — | Stratix II |
| Logic Elements | — | 33,880 |
| Logic Array Blocks (LABs) | — | 1,694 |
| Embedded Multipliers (DSP blocks) | — | 12 DSP blocks |
| Maximum User I/Os | — | 500 |
| Core Voltage | — | 1.2 V |
| Maximum Operating Frequency | — | 609.76 MHz |
| Speed Grade | — | C5 (moderate-speed bin) |
| Operating Temperature (Commercial) | — | 0C to 85C junction |
| Type de mémoire | — | TriMatrix (M512 / M4K / M-RAM) |