EP3SE260H780C4 vs EP3SE260H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SE260H780C4 par Intel et EP3SE260H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE260H780C4 - Stratix III E FPGA, 255K LE, 780-FCBGA | Intel / Altera
EP3SE260H780C4 ObsoleteIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ ActifComparaison des spécifications
| Paramètre | EP3SE260H780C4 | EP3SE260H780C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3 150,00 | $1 325,00 |
| Family | Stratix III E | — |
| Logic Elements | 255,000 | — |
| Total Memory Bits | 16,672,640 bits | — |
| Logic Array Blocks (LABs) | 10,200 | — |
| User I/Os | 488 | 488 |
| Embedded Multipliers (18x18) | 576 | — |
| Distributed Memory | 1,020 Kbits | — |
| Number of PLLs | 8 | — |
| Core Voltage | 0.9 V | — |
| Auxiliary Voltage | 1.1 V | — |
| Process Technology | 65 nm | 40 nm CMOS |
| Speed Grade | C4 | — |
| Boîtier | 780-ball FCBGA (H780) | 780-BBGA, FCBGA (H780) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | Compliant (lead-free 'N' suffix) |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Température de fonctionnement | — | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Niveau de sensibilité à l'humidité (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |