EP3SL200H780C4L vs EP3SL200H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SL200H780C4L par Intel et EP3SL200H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP3SL200H780C4L | EP3SL200H780C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $6 459,35 | $4 995,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix III | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory | 6.5 Mbit | — |
| User I/O Count | 488 | — |
| Package Type | 780-ball FCBGA (FineLine BGA, HBGA) | — |
| Package Code | BGA-780 / PBGA780 / HBGA-780 | — |
| Package Mounting | Surface Mount | — |
| Internal Logic Frequency | up to 717 MHz (per ampheo datasheet brief) | — |
| Speed Grade | -4 (medium performance, commercial) | C3 (commercial, -3 speed) |
| Température de fonctionnement | 0C to 85C (commercial) | 0C to +85C (commercial) |
| Lead-Free / Pb-Free | Yes (L suffix, lead-free) | — |
| Statut RoHS | Compliant | — |
| Process Technology | TSMC 40 nm | — |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| Family | — | Stratix III L (low-power) |
| Process Node | — | 40 nm |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Boîtier | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Type de montage | — | Surface Mount |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| Niveau MSL | — | 3 |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |