EP3SL200H780C4L vs EP3SL200H780C3N Vergleich
Detaillierter Direktvergleich von EP3SL200H780C4L von Intel und EP3SL200H780C3N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SL200H780C4L | EP3SL200H780C3N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6.459,35 | $4.995,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix III | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory | 6.5 Mbit | — |
| User I/O Count | 488 | — |
| Package Type | 780-ball FCBGA (FineLine BGA, HBGA) | — |
| Package Code | BGA-780 / PBGA780 / HBGA-780 | — |
| Package Mounting | Surface Mount | — |
| Internal Logic Frequency | up to 717 MHz (per ampheo datasheet brief) | — |
| Speed Grade | -4 (medium performance, commercial) | C3 (commercial, -3 speed) |
| Betriebstemperatur | 0C to 85C (commercial) | 0C to +85C (commercial) |
| Lead-Free / Pb-Free | Yes (L suffix, lead-free) | — |
| RoHS-Status | Compliant | — |
| Process Technology | TSMC 40 nm | — |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| Family | — | Stratix III L (low-power) |
| Process Node | — | 40 nm |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Gehäuse | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Montageart | — | Surface Mount |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| MSL-Level | — | 3 |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |