EP610DC-35 vs EP610DC-20 Comparaison
Comparaison détaillée côte à côte de EP610DC-35 par Altera et EP610DC-20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-35 | EP610DC-20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,40 | $15,85 |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | Classic EP610 |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 22 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS | CMOS, UV-erasable floating gate |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Boîtier | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Type de montage | Through-Hole (DIP) | Through-hole |
| Température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0 °C to 70 °C (commercial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| Statut RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Programming Method | — | UV erasure + parallel programmer |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |