EP910DC-35 vs EP910IDI-15 Comparaison
Comparaison détaillée côte à côte de EP910DC-35 par Altera et EP910IDI-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910DC-35 | EP910IDI-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,95 | $29,00 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | CPLD (Complex Programmable Logic Device) |
| Family | Classic EPLD EP910 | Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Fréquence d'horloge maximale | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | -40C to +85C (industrial, "I" grade) |
| Boîtier | 40-pin CDIP (Ceramic DIP) with quartz window | 40-pin CDIP (CerDIP) with quartz window |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS EPROM |
| Statut RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Logic Gates | — | 450 gates |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Type de montage | — | Through-hole (DIP) |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |