EP910DC-35 vs EP910IDI-15 对比
详细并排对比 EP910DC-35 出自 Altera 和 EP910IDI-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DC-35 | EP910IDI-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.95 | $29.00 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | CPLD (Complex Programmable Logic Device) |
| Family | Classic EPLD EP910 | Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| 最大时钟频率 | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| 工作温度 | 0 °C to +70 °C (commercial) | -40C to +85C (industrial, "I" grade) |
| 封装 | 40-pin CDIP (Ceramic DIP) with quartz window | 40-pin CDIP (CerDIP) with quartz window |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS EPROM |
| RoHS 状态 | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Logic Gates | — | 450 gates |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| 安装类型 | — | Through-hole (DIP) |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |