EP910DC-35 vs EP910IDI-15 비교

다음의 상세 나란히 비교: EP910DC-35 제조: Altera 및 EP910IDI-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910DC-35 EP910IDI-15
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $10.95 $29.00
Device Type UV-Erasable CMOS PLD (PAL-type) CPLD (Complex Programmable Logic Device)
Family Classic EPLD EP910 Classic EPLD
Architecture PAL-type sum-of-products AND-OR array —
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 —
Dedicated Inputs 12 —
I/O Pins 24 —
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
최대 클록 주파수 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) 5 V
동작 온도 0 °C to +70 °C (commercial) -40C to +85C (industrial, "I" grade)
패키지 40-pin CDIP (Ceramic DIP) with quartz window 40-pin CDIP (CerDIP) with quartz window
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase —
Technology CMOS, UV-erasable EPROM cell CMOS EPROM
RoHS 상태 Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Logic Gates — 450 gates
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Program/Erase Method — UV-erasable windowed CerDIP
실장 유형 — Through-hole (DIP)
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

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