EP910ILC-15N vs EP910DC-15 Comparaison
Comparaison détaillée côte à côte de EP910ILC-15N par Altera et EP910DC-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Comparaison des spécifications
| Paramètre | EP910ILC-15N | EP910DC-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,85 | $10,75 |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| Boîtier | PLCC-44 (J-lead, surface mount) | 24-pin ceramic DIP (DC) |
| Type de montage | Surface Mount | Through-Hole |
| Température de fonctionnement | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Statut RoHS | Compliant | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |