EP910ILC-25 vs EP910DM-40 Comparaison
Comparaison détaillée côte à côte de EP910ILC-25 par Intel et EP910DM-40 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910ILC-25 | EP910DM-40 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $21,00 |
| Family | EP910 Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 40 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Boîtier | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Type de montage | Surface Mount | Through-Hole (DIP) |
| Température de fonctionnement | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Tension d'alimentation | 5 V | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Statut RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| Statut du cycle de vie | Obsolete - last time buy was late 1990s | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |