EP910ILC-25 vs EP910DM-40 Comparison
Detailed side-by-side comparison of EP910ILC-25 by Intel and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-25 | EP910DM-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 40 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Package | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Mounting Type | Surface Mount | Through-Hole (DIP) |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | 5 V | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle Status | Obsolete - last time buy was late 1990s | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |