EP910ILC-25 vs EP910DM-40 比較
詳細な並列比較: EP910ILC-25 メーカー: Intel および EP910DM-40 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILC-25 | EP910DM-40 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $21.00 |
| Family | EP910 Classic EPLD | Altera Classic EP910 |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 40 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| パッケージ | 44-pin JLCC (windowed ceramic) | 40-pin Ceramic DIP (Cerdip) with UV window |
| 実装タイプ | Surface Mount | Through-Hole (DIP) |
| 動作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 電源電圧 | 5 V | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS ステータス | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| ライフサイクル状態 | Obsolete - last time buy was late 1990s | — |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | — | 36 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |