EP910PI-15T vs EP910PC-20T Comparaison
Comparaison détaillée côte à côte de EP910PI-15T par Altera et EP910PC-20T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PI-15T | EP910PC-20T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Unknown |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,95 | $8,70 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Classic EPLD |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Tension d'alimentation | 4.5 V to 5.5 V (5 V nominal) | [DATA_NEEDED: operating supply voltage] |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | — |
| Boîtier | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | — |
| Type de montage | Through-Hole | — |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial temp range] | [DATA_NEEDED: operating temperature range] |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| Statut RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | unknown |
| Device Type | — | EPLD |
| Fabrication Technology | — | CMOS |
| Logic Integration | — | 300 to 900 usable gates |
| Logic Emulation | — | 100% TTL emulation |
| Application Function | — | High-speed, low-power logic integration |
| Programmable Device Class | — | Erasable programmable logic device |
| Device Family | — | Altera Classic EPLD Family |
| Speed Grade | — | 20 ns |
| Package Code | — | PC |
| Package Pin Count | — | [DATA_NEEDED: package pin count] |
| Package Dimensions | — | [DATA_NEEDED: package dimensions] |
| I/O Count | — | [DATA_NEEDED: I/O count] |
| Internal Logic Capacity | — | 300 to 900 usable gates |
| Supported Logic Integration | — | Multiple PAL- and GAL-type devices |
| Programming Interface | — | [DATA_NEEDED: programming interface] |
| Programming Voltage | — | [DATA_NEEDED: programming voltage] |
| Mounting Technology | — | [DATA_NEEDED: mounting technology] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |