EP910PI-15T vs EP910PC-20T Comparación
Comparación detallada lado a lado de EP910PI-15T por Altera y EP910PC-20T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-15T | EP910PC-20T |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Unknown |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $8,70 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Classic EPLD |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Tensión de alimentación | 4.5 V to 5.5 V (5 V nominal) | [DATA_NEEDED: operating supply voltage] |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | — |
| Encapsulado | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | — |
| Tipo de montaje | Through-Hole | — |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial temp range] | [DATA_NEEDED: operating temperature range] |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| Estado RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | unknown |
| Device Type | — | EPLD |
| Fabrication Technology | — | CMOS |
| Logic Integration | — | 300 to 900 usable gates |
| Logic Emulation | — | 100% TTL emulation |
| Application Function | — | High-speed, low-power logic integration |
| Programmable Device Class | — | Erasable programmable logic device |
| Device Family | — | Altera Classic EPLD Family |
| Speed Grade | — | 20 ns |
| Package Code | — | PC |
| Package Pin Count | — | [DATA_NEEDED: package pin count] |
| Package Dimensions | — | [DATA_NEEDED: package dimensions] |
| I/O Count | — | [DATA_NEEDED: I/O count] |
| Internal Logic Capacity | — | 300 to 900 usable gates |
| Supported Logic Integration | — | Multiple PAL- and GAL-type devices |
| Programming Interface | — | [DATA_NEEDED: programming interface] |
| Programming Voltage | — | [DATA_NEEDED: programming voltage] |
| Mounting Technology | — | [DATA_NEEDED: mounting technology] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |