EPC16QC100N vs EPC16QI100TBAC Comparaison
Comparaison détaillée côte à côte de EPC16QC100N par Altera et EPC16QI100TBAC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPC16QC100N | EPC16QI100TBAC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,10 | $15,95 |
| Taille de mémoire | 16 Mbit (16,777,216 bits) | — |
| Programmable Type | In System Programmable | — |
| Configuration Clock Frequency | 33 MHz max | — |
| On-Chip Decompression | Yes (supports compressed bitstreams) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Access Time | 90 ns typical | — |
| Flash Read Bandwidth | 160 Mbps (16-bit DQ at 10 MHz) | — |
| Configuration Interface | FPP / PS / AS via dedicated FPGA pins | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Température de fonctionnement | 0 C to 70 C | -40C to +85C (industrial) |
| Boîtier | 100-pin PQFP (20 x 14 mm) | 100-pin PQFP (20 x 14 mm) |
| Type de montage | Surface Mount | Surface Mount (PQFP) |
| Lead Free | Yes (per datasheet) | — |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | Altera Stratix, Cyclone, Arria series |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Type de mémoire | — | Flash (Enhanced Configuration Device) |
| Tension d'alimentation | — | 3.3 V |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Maximum Configuration Clock | — | 40 MHz |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan and programming) |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| Niveau MSL | — | 3 (168 hours) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Configuration Controller | — | Integrated |
| Programming Interface | — | JTAG / 4-wire passive serial |