EPC16QI100TBAC vs EPC18QI100 Comparaison
Comparaison détaillée côte à côte de EPC16QI100TBAC par Altera et EPC18QI100 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPC16QI100TBAC | EPC18QI100 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,95 | $10,40 |
| Memory Density | 16 Mbit (2 Mbyte) | 18 Mbit (18,874,368 bits) |
| Type de mémoire | Flash (Enhanced Configuration Device) | — |
| Tension d'alimentation | 3.3 V | — |
| Configuration Modes | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) | — |
| Maximum Configuration Clock | 40 MHz | — |
| Number of Configuration Pages | Up to 8 (selectable via PGM[2..0]) | — |
| Boîtier | 100-pin PQFP (20 x 14 mm) | 100-pin PQFP (Plastic Quad Flat Pack) |
| In-System Programmable | Yes (via JTAG / IEEE 1149.1) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan and programming) | — |
| Supported FPGA Families | Altera Stratix, Cyclone, Arria series | — |
| Data Compression | Supported (15-30% density gain depending on target FPGA) | — |
| Température de fonctionnement | -40C to +85C (industrial) | — |
| Type de montage | Surface Mount (PQFP) | Surface Mount |
| Niveau MSL | 3 (168 hours) | [DATA_NEEDED: MSL level] |
| Lead-Free / RoHS | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] | — |
| Dynamic Reconfiguration | Yes (page mode via PGM[2..0] pins) | — |
| Configuration Controller | Integrated | — |
| Programming Interface | JTAG / 4-wire passive serial | JTAG (IEEE 1149.1) in-system programmable |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Device Type | — | FPGA Configuration PROM (nonvolatile) |
| Configuration Interface | — | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5 V tolerant |
| Cascading Support | — | Yes (via nCASC pin, multi-device chains supported) |
| Package Dimensions | — | 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads) |
| Plage de température de fonctionnement | — | -40 C to +85 C (industrial) |
| Lead Finish | — | Matte tin (lead-free, per Altera Pb-free roadmap) |
| Statut RoHS | — | Compliant (Pb-free part marking) |
| Configuration Time | — | [DATA_NEEDED: configuration time at typical DCLK] |
| End-of-Life Status | — | Obsolete; replaced by Altera/Intel EPCQ family |