EPC16QI100TBAC vs EPC18QI100 比較

詳細な並列比較: EPC16QI100TBAC メーカー: Altera および EPC18QI100 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

Altera
EPC16QI100TBAC EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC ⚠ ラストタイムバイ

仕様比較

パラメータ EPC16QI100TBAC EPC18QI100
ブランド Altera Altera
カテゴリ Memory ICs Memory ICs
ライフサイクル状態 ラストバイ Obsolete
在庫状況 In Stock In Stock
単価(USD) $15.95 $10.40
Memory Density 16 Mbit (2 Mbyte) 18 Mbit (18,874,368 bits)
メモリタイプ Flash (Enhanced Configuration Device) —
電源電圧 3.3 V —
Configuration Modes Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) —
Maximum Configuration Clock 40 MHz —
Number of Configuration Pages Up to 8 (selectable via PGM[2..0]) —
パッケージ 100-pin PQFP (20 x 14 mm) 100-pin PQFP (Plastic Quad Flat Pack)
In-System Programmable Yes (via JTAG / IEEE 1149.1) —
JTAG Support Yes (IEEE 1149.1 boundary-scan and programming) —
Supported FPGA Families Altera Stratix, Cyclone, Arria series —
Data Compression Supported (15-30% density gain depending on target FPGA) —
動作温度 -40C to +85C (industrial) —
実装タイプ Surface Mount (PQFP) Surface Mount
MSLレベル 3 (168 hours) [DATA_NEEDED: MSL level]
Lead-Free / RoHS Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] —
Dynamic Reconfiguration Yes (page mode via PGM[2..0] pins) —
Configuration Controller Integrated —
Programming Interface JTAG / 4-wire passive serial JTAG (IEEE 1149.1) in-system programmable
Manufacturer — Altera (now Intel Programmable Solutions Group)
Device Type — FPGA Configuration PROM (nonvolatile)
Configuration Interface — Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 5 V tolerant
Cascading Support — Yes (via nCASC pin, multi-device chains supported)
Package Dimensions — 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads)
動作温度範囲 — -40 C to +85 C (industrial)
Lead Finish — Matte tin (lead-free, per Altera Pb-free roadmap)
RoHS ステータス — Compliant (Pb-free part marking)
Configuration Time — [DATA_NEEDED: configuration time at typical DCLK]
End-of-Life Status — Obsolete; replaced by Altera/Intel EPCQ family

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